参数资料
型号: PIC18F452-E/ML
厂商: Microchip Technology
文件页数: 109/134页
文件大小: 0K
描述: IC MCU FLASH 16KX16 A/D 44QFN
产品培训模块: Asynchronous Stimulus
标准包装: 45
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 管件
PIC16C9XX
DS30444E - page 76
1997 Microchip Technology Inc.
11.3.1.3
TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will be
sent on the ninth bit, and pin RC3/SCK/SCL is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP
(SSPCON<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA signal
is valid during the SCL high time (Figure 11-20).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status of
the byte. Flag bit SSPIF is set on the falling edge of the
ninth clock pulse.
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also
loads
the
SSPSR
register.
Then
pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 11-20: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Transmitting Data
R/W = 1
Receiving Address
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
Set bit after writing to SSPBUF
S
Data in
sampled
SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
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