参数资料
型号: PIC18F4520-E/ML
厂商: Microchip Technology
文件页数: 41/151页
文件大小: 0K
描述: IC MCU FLASH 16KX16 44QFN
产品培训模块: Asynchronous Stimulus
标准包装: 45
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 25MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 13x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 管件
PIC16(L)F1782/3
DS41579C-page 308
Preliminary
2011-2012 Microchip Technology Inc.
26.6.13.2
Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a)
A low level is sampled on SDA when SCL goes
from low level to high level.
b)
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to zero. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 26-35).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 26-36:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 26-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared by software
’0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
by software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG
’0’
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