参数资料
型号: PIC18F6493T-I/PT
厂商: Microchip Technology
文件页数: 29/41页
文件大小: 0K
描述: IC PIC MCU FLASH 8KX16 64TQFP
产品培训模块: Asynchronous Stimulus
标准包装: 1,200
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,LCD,POR,PWM,WDT
输入/输出数: 50
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 12x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
其它名称: PIC18F6493T-I/PTTR
2010 Microchip Technology Inc.
DS39896C-page 35
PIC18F6393/6493/8393/8493
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets and
is not affected by any other Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to perform an A/D
conversion:
1.
Configure the A/D module:
Configure analog pins, voltage reference and
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D acquisition time (ADCON2)
Select A/D conversion clock (ADCON2)
Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time (if required).
4.
Start conversion:
Set GO/DONE bit (ADCON0<1>)
5.
Wait for A/D conversion to complete by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7.
For the next conversion, go to Step 1 or Step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 2-2:
A/D TRANSFER FUNCTION
FIGURE 2-3:
ANALOG INPUT MODEL
Dig
ita
lCo
de
Ou
tp
u
t
FFEh
003h
002h
001h
000h
0.
5L
S
B
1L
S
B
1.
5L
S
B
2L
S
B
2.
5L
S
B
40
94
LS
B
40
94.
5L
S
B
3L
S
B
Analog Input Voltage
FFFh
40
95
LS
B
40
95.
5L
S
B
VAIN
CPIN
Rs
ANx
5 pF
VT = 0.6V
ILEAKAGE
RIC
1k
Sampling
Switch
SS
RSS
CHOLD = 25 pF
VSS
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch Resistance
RSS
VDD
6V
Sampling Switch
5V
4V
3V
2V
12
3
4
(k
)
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