参数资料
型号: PIC18F66J93T-I/PT
厂商: Microchip Technology
文件页数: 39/54页
文件大小: 0K
描述: IC PIC MCU FLASH 64KB 64-TQFP
产品培训模块: PIC18 J Series MCU Overview
标准包装: 1,200
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,LCD,LVD,POR,PWM,WDT
输入/输出数: 51
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 3923 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 12x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
PIC18F87J93 FAMILY
DS39948A-page 42
Preliminary
2009 Microchip Technology Inc.
FIGURE 4-3:
A/D CONVERSION TIMING
TABLE 4-2:
A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
0.8
12.5(1)
μsTOSC based, VREF ≥ 3.0V
131
TCNV
Conversion Time
(not including acquisition time)(2)
13
14
TAD
132
TACQ
Acquisition Time(3)
1.4
μs
135
TSWC
Switching Time from Convert
→ Sample
(Note 4)
137
TDIS
Discharge Time
0.2
μs
Note 1:
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2:
ADRES registers may be read on the following TCY cycle.
3:
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50
Ω.
4:
On the following cycle of the device clock.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
11
10
9
3
2
1
Note
1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
TCY
0
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