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| 型号： | PIC18F66K22T-I/MR |
| 厂商： | Microchip Technology |
| 文件页数： | 27/61页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 64KB FLASH 64QFN |
| 标准包装： | 3,300 |
| 系列： | PIC® XLP™ 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 64MHz |
| 连通性： | I²C，LIN，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，LVD，POR，PWM，WDT |
| 输入/输出数： | 53 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 数据转换器： | A/D 16x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
33 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
The device exits Idle mode through either a system interrupt or a hardware reset. Exiting
Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle
mode. After exit the Interrupt Service Routine, the interrupted program resumes execution
beginning at the instruction immediately following the instruction which invoked the Idle
mode. A hardware reset starts the device similar to a power-on reset.
6.12.2 Power-down mode
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for level
sensitive interrupts only. SRAM contents are retained during Power-down, the minimum
VDD level is 2.0 V.
The device exits Power-down mode through either an enabled external level sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
Power-down. Holding the external interrupt pin LOW restarts the oscillator, the signal must
hold LOW at least 1024 clock cycles before bringing back HIGH to complete the exit.
Upon interrupt signal restored to logic VIH, the interrupt service routine program execution
resumes beginning at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of Power-down, the reset or external interrupt should not be executed
before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage
long enough at its normal operating level for the oscillator to restart and stabilize (normally
less than 10 ms).
6.13 Data EEPROM
The P89V52X2 contains 192 B of data EEPROM organized into three pages of 64 B
each. This memory can be erased in 64 byte pages (using a Page Erase command) or
erased and written as bytes. The P89V52X2 ash reliably stores memory contents even
after 100000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. P89V52X2 uses VDD as the supply voltage to perform the
Program/Erase algorithms.
Table 31.
Power-saving modes
Mode
Initiated by
State of device
Exited by
Idle mode
Software (set IDL bit in
PCON)
MOV PCON, #01H;
CLK is running. Interrupts,
serial port and timers/counters
are active. Program Counter is
stopped. ALE and PSEN
signals at a HIGH-level during
Idle. All registers remain
unchanged.
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode,
after the interrupt service routine RETI
instruction, program resumes execution
beginning at the instruction following the one
that invoked Idle mode. A hardware reset
restarts the device similar to a power-on
reset.
Power-down
mode
Software (set PD bit in
PCON)
MOV PCON, #02H;
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW-level during power-down.
External Interrupts are only
active for level sensitive
interrupts, if enabled.
Enabled external level sensitive interrupt or
hardware reset. Start of interrupt clears PD
bit and exits Power-down mode, after the
interrupt service routine RETI instruction
program resumes execution beginning at
the instruction following the one that invoked
Power-down mode. A hardware reset
restarts the device similar to a power-on
reset.
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