参数资料
型号: PIC18F66K90T-I/PTRSL
厂商: Microchip Technology
文件页数: 16/110页
文件大小: 0K
描述: MCU 8BIT 64K FLASH 64-TQFP
标准包装: 1,200
系列: PIC® XLP™ 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 64MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,LCD,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 16x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
2010 Microchip Technology Inc.
Preliminary
DS39964B-page 463
PIC18F47J53 FAMILY
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
ffff
None
1, 2
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n, s
n
n
s
k
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call Subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address
1st word
2nd word
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
Software Device Reset
Return from Interrupt Enable
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
1 (2)
2
1 (2)
2
1
2
1
2
1
2
1
1110
1101
1110
1111
0000
1110
1111
0000
1111
0000
1101
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
1111
kkkk
0000
xxxx
0000
1nnn
0000
1100
0000
nnnn
kkkk
0000
kkkk
0000
xxxx
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
kkkk
0100
0111
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
TO, PD
C
None
All
GIE/GIEH,
PEIE/GIEL
None
TO, PD
4
TABLE 29-2:
PIC18F47J53 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
Status
Affected
Notes
MSb
LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
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