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参数资料
型号： PIC18F67K90-I/MRRSL
厂商： Microchip Technology
文件页数： 34/110页
文件大小： 0K
描述： MCU PIC 128K FLASH XLP 64QFN
产品培训模块： 8-bit PIC® Microcontroller Portfolio
标准包装： 40
系列： PIC® XLP™ 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 64MHz
连通性： I²C，LIN，SPI，UART/USART
外围设备： 欠压检测/复位，LCD，POR，PWM，WDT
输入/输出数： 53
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 4K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
数据转换器： A/D 16x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-VFQFN 裸露焊盘
包装： 托盘
2010 Microchip Technology Inc.
Preliminary
DS39964B-page 481
PIC18F47J53 FAMILY
INCFSZ
Increment f, Skip if 0
Syntax:
INCFSZ
f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
(f) + 1 dest,
skip if result = 0
Status Affected:
None
Encoding:
0011
11da
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
INCFSZ
CNT, 1, 0
NZERO
:
ZERO
:
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
=
CNT + 1
If CNT
=
0;
PC
=
Address (ZERO)
If CNT
0;
PC
=
Address (NZERO)
INFSNZ
Increment f, Skip if Not 0
Syntax:
INFSNZ
f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
(f) + 1 dest,
skip if result
0
Status Affected:
None
Encoding:
0100
10da
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
INFSNZ
REG, 1, 0
ZERO
NZERO
Before Instruction
PC
=
Address (HERE)
After Instruction
REG
=
REG + 1
If REG
0;
PC
=
Address (NZERO)
If REG
=
0;
PC
=
Address (ZERO)
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