参数资料
型号: PIC18F8620-E/PT
厂商: Microchip Technology
文件页数: 140/165页
文件大小: 0K
描述: IC PIC MCU FLASH 32KX16 80TQFP
产品培训模块: Asynchronous Stimulus
标准包装: 119
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 25MHz
连通性: EBI/EMI,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 68
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 3.75K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 16x10b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 80-TQFP
包装: 托盘
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 74
2004 Microchip Technology Inc.
6.2.2
16-BIT WORD WRITE MODE
Figure 6-2 shows an example of 16-bit Word Write
mode for PIC18F8X20 devices. This mode is used for
word-wide memories, which includes some of the
EPROM and Flash type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWT cycles to even or odd addresses.
During
a
TBLWT
cycle
to
an
even
address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
During
a
TBLWT
cycle
to
an
odd
address
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of TBLPTR, but it is left unconnected. Instead,
the UB and LB signals are active to select both bytes.
The obvious limitation to this method is that the table
write must be done in pairs on a specific word boundary
to correctly write a word location.
FIGURE 6-2:
16-BIT WORD WRITE MODE EXAMPLE
AD<7:0>
PIC18F8X20
AD<15:8>
ALE
373
A<20:1>
373
OE
WRH
A<19:16>
A<x:0>
D<15:0>
OE
WR(1)
CE
D<15:0>
JEDEC Word
EPROM Memory
Address Bus
Data Bus
Control Lines
Note 1:
This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
CE
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