参数资料
型号: PIC18F8628T-I/PT
厂商: Microchip Technology
文件页数: 28/60页
文件大小: 0K
描述: IC PIC MCU FLASH 48KX16 80TQFP
产品培训模块: Asynchronous Stimulus
标准包装: 1,200
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: EBI/EMI,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 70
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 3.8K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 16x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-TQFP
包装: 带卷 (TR)
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
其它名称: PIC18F8628T-I/PTTR
PIC18F8723 FAMILY
DS39894B-page 34
2009 Microchip Technology Inc.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 2-1.
FIGURE 2-1:
A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
Reference
Voltage
AVDD(2)
VCFG1:VCFG0
CHS3:CHS0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
0111
0110
0101
0100
0011
0010
0001
0000
12-Bit
A/D
VREF-
AVSS(2)
Converter
AN12(1)
AN11
AN10
AN9
AN8
1100
1011
1010
1001
1000
Note 1: Channels AN12 through AN15 are not available on PIC18F6628/6723 devices.
2: I/O pins have diode protection to VDD and VSS.
0X
1X
X
1
X
0
AN15(1)
AN14(1)
AN13(1)
1111
1110
1101
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