参数资料
型号: PIC18F86J11T-I/PT
厂商: Microchip Technology
文件页数: 80/107页
文件大小: 0K
描述: IC PIC MCU FLASH 32KX16 80TQFP
产品培训模块: Asynchronous Stimulus
PIC18 J Series MCU Overview
标准包装: 1,200
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: EBI/EMI,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 68
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 3930 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 15x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-TQFP
包装: 带卷 (TR)
配用: AC162091-ND - HEADER MPLAB ICD2 18F87J11 64/80
MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
AC164328-ND - MODULE SKT FOR 80TQFP
其它名称: PIC18F86J11T-I/PTTR
PIC18F87J11 FAMILY
DS39778E-page 74
2007-2012 Microchip Technology Inc.
6.2
PIC18 Instruction Cycle
6.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping, quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the Program Counter
is incremented on every Q1. The instruction is fetched
from the program memory and latched into the Instruc-
tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
6.2.2
INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the Program Counter to change
(e.g., GOTO), then two cycles are required to complete
the instruction (Example 6-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 6-5:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 6-3:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC
PC + 2
PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. BRA SUB_1
Fetch 3
Execute 3
4. BSF
PORTA, BIT3 (Forced NOP)
Fetch 4
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
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