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| 型号： | PIC18F86J50T-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 28/61页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 32KX16 80TQFP |
| 产品培训模块： | Asynchronous Stimulus PIC18 J Series MCU Overview |
| 标准包装： | 1,200 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 48MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART，USB |
| 外围设备： | 欠压检测/复位，LVD，POR，PWM，WDT |
| 输入/输出数： | 65 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 3.8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 数据转换器： | A/D 12x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 80-TQFP |
| 包装： | 带卷 (TR) |
| 配用： | AC162087-ND - HEADER MPLAB ICD2 18F87J50 68/84 MA180021-ND - MODULE PLUG-IN 18F87J50 FS USB AC164328-ND - MODULE SKT FOR 80TQFP |
| 其它名称： | PIC18F86J50T-I/PTTR |
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Philips Semiconductors
Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
31
Timer/Counters
The P87LPC767 has two general purpose counter/timers which are
upward compatible with the standard 80C51 Timer 0 and Timer 1.
Both can be configured to operate either as timers or event counters
(see Figure 24). An option to automatically toggle the T0 and/or T1
pins upon timer overflow has been added.
In the “Timer” function, the register is incremented every machine
cycle. Thus, one can think of it as counting machine cycles. Since a
machine cycle consists of 6 CPU clock periods, the count rate is 1/6
of the CPU clock frequency. Refer to the section Enhanced CPU for
a description of the CPU clock.
In the “Counter” function, the register is incremented in response to
a 1-to-0 transition at its corresponding external input pin, T0 or T1.
In this function, the external input is sampled once during every
machine cycle. When the samples of the pin state show a high in
one cycle and a low in the next cycle, the count is incremented. The
new count value appears in the register during the cycle following
the one in which the transition was detected. Since it takes 2
machine cycles (12 CPU clocks) to recognize a 1-to-0 transition, the
maximum count rate is 1/6 of the CPU clock frequency. There are no
restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes,
it should be held for at least one full machine cycle.
The “Timer” or “Counter” function is selected by control bits C/T in
the Special Function Register TMOD. In addition to the “Timer” or
“Counter” selection, Timer 0 and Timer 1 have four operating
modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0,
1, and 2 are the same for both Timers/Counters. Mode 3 is different.
The four operating modes are described in the following text.
BIT
SYMBOL
FUNCTION
TMOD.7
GATE
Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is high and
the TR1 control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set.
TMOD.6
C/T
Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from internal system clock.)
Set for Counter operation (input from T1 input pin).
TMOD.5, 4
M1, M0
Mode Select for Timer 1 (see table below).
TMOD.3
GATE
Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0 pin is high and
the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set.
TMOD.2
C/T
Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from internal system clock.)
Set for Counter operation (input from T0 input pin).
TMOD.1, 0
M1, M0
Mode Select for Timer 0 (see table below).
M1, M0
Timer Mode
0 0
8048 Timer “TLn” serves as 5-bit prescaler.
0 1
16-bit Timer/Counter “THn” and “TLn” are cascaded; there is no prescaler.
1 0
8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.
1 1
Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see
text). Timer 1 in this mode is stopped.
M0
SU01171
M1
C/T
GATE
M0
M1
C/T
GATE
0
1
2
3
4
5
6
7
TMOD
Reset Value: 00h
Not Bit Addressable
Address: 89h
T1
T0
Figure 24. Timer/Counter Mode Control Register (TMOD)
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