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参数资料
型号： PIC18F8720-E/PT
厂商： Microchip Technology
文件页数： 107/165页
文件大小： 0K
描述： IC PIC MCU FLASH 64KX16 80TQFP
产品培训模块： Asynchronous Stimulus
标准包装： 119
系列： PIC® 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 25MHz
连通性： EBI/EMI，I²C，SPI，UART/USART
外围设备： 欠压检测/复位，LVD，POR，PWM，WDT
输入/输出数： 68
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 3.75K x 8
电压 - 电源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
数据转换器： A/D 16x10b
振荡器型： 外部
工作温度： -40°C ~ 125°C
封装/外壳： 80-TQFP
包装： 托盘
配用： XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 44
2004 Microchip Technology Inc.
4.3
Fast Register Stack
A “fast interrupt return” option is available for interrupts.
A Fast Register Stack is provided for the Status, WREG
and BSR registers and is only one in depth. The stack
is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters, if the FAST RETURN instruction is used to return
from the interrupt.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
If high priority interrupts are not disabled during low
priority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
4.4
PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits
wide. The low byte is called the PCL register; this reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable; updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable; updates to the PCU register may
be performed through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of the PCL is fixed to a value of
‘0’. The PC increments by 2 to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1
“Computed GOTO”).
4.5
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC
PC+2
PC+4
Fetch INST (PC)
Execute INST (PC-2)
Fetch INST (PC+2)
Execute INST (PC)
Fetch INST (PC+4)
Execute INST (PC+2)
Internal
Phase
Clock
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相关代理商/技术参数
参数描述
PIC18F8720-I/PT 功能描述:8位微控制器 -MCU 128KB 3840 RAM 68I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC18F8720-I/PT 制造商:Microchip Technology Inc 功能描述:IC 8BIT FLASH MCU 18F8720 TQFP80
PIC18F8720-I/PTC01 功能描述:IC PIC MCU FLASH 64KX16 80TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:PIC® 18F 产品培训模块:XLP Deep Sleep Mode 8-bit PIC® Microcontroller Portfolio 标准包装:22 系列:PIC® XLP™ 18F 核心处理器:PIC 芯体尺寸:8-位 速度:48MHz 连通性:I²C，SPI，UART/USART，USB 外围设备:欠压检测/复位，POR，PWM，WDT 输入/输出数:14 程序存储器容量:8KB（4K x 16） 程序存储器类型:闪存 EEPROM 大小:256 x 8 RAM 容量:512 x 8 电压 - 电源 (Vcc/Vdd):1.8 V ~ 5.5 V 数据转换器:A/D 11x10b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:20-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:642 (CN2011-ZH PDF) 配用:DV164126-ND - KIT DEVELOPMENT USB W/PICKIT 2DM164127-ND - KIT DEVELOPMENT USB 18F14/13K50AC164112-ND - VOLTAGE LIMITER MPLAB ICD2 VPP
PIC18F8720T-E/PT 功能描述:8位微控制器 -MCU 25MHz 128KB Flash RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC18F8720T-I/PT 功能描述:8位微控制器 -MCU 128KB 3840 RAM 68I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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