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参数资料
| 型号： | PIC18F97J60-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 64KX16 100TQFP |
| 产品培训模块： | Embedded Ethernet Asynchronous Stimulus PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 标准包装： | 119 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 41.667MHz |
| 连通性： | EBI/EMI，以太网，I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 70 |
| 程序存储器容量： | 128KB（64K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 3808 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 包装： | 托盘 |
| 产品目录页面： | 645 (CN2011-ZH PDF) |
| 配用： | AC162064-ND - HEADER INTFC MPLABICD2 64/80/100 DM163024-ND - BOARD DEMO PICDEM.NET 2 AC164323-ND - MODULE SKT FOR 100TQFP |
PIC18F97J60 FAMILY
DS80292D-page 2
2008 Microchip Technology Inc.
3.
Module: I/O (PORTJ) and External
Memory Bus
In
an
Extended
Microcontroller
mode
(CONFIG3L<EMB1:0> = 00, 01 or 10), each
control signal on PORTJ is supposed to be driven
to its Idle state. However, the control signals on
PORTJ pins go to a high-impedance state for a
brief interval after a MCLR Reset. The brief loss of
control signals may cause the corruption of data in
memory devices connected to the External
Memory Bus (EMB).
Work around
To maintain the default states on the control lines,
use pull-up or pull-down resistors on all PORTJ
pins (pull-down on PORTJ<4,0>, pull-up on all
others).
Date Codes that pertain to this issue:
All engineering and production devices.
4.
Module: Ethernet (Buffer Memory)
The receive hardware may corrupt the circular
receive buffer (including the Next Packet Pointer
and receive status vector fields) when an even value
is programmed into the ERXRDPTH:ERXRDPTL
registers.
Work around
Ensure that only odd addresses are written to the
ERXRDPT registers. Assuming that ERXND con-
tains an odd value, many applications can derive a
suitable value to write to ERXRDPT by subtracting 1
from the Next Packet Pointer (a value always
ensured to be even because of hardware padding)
and then compensating for a potential ERXST to
ERXND wraparound.
Assuming that the receive buffer area does not
span the 1FFFh to 0000h memory boundary, the
logic in Example 1 will ensure that ERXRDPT is
programmed with an odd value.
EXAMPLE 1:
Date Codes that pertain to this issue:
All engineering and production devices.
Note:
This issue is only applicable to the
100-pin device.
if (Next Packet Pointer – 1 < ERXST) or
(Next Packet Pointer – 1 > ERXND)
then:
ERXRDPT = ERXND
else:
ERXRDPT = Next Packet Pointer – 1
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