
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 89
PIC18C601/801
8.0
INTERRUPTS
PIC18C601/801 devices have 15 interrupt sources and
an interrupt priority feature that allows each interrupt
source to be assigned a high priority level, or a low pri-
ority level. The high priority interrupt vector is at
000008h and the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are 10 registers that are used to control interrupt
operation. These registers are:
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files sup-
plied with MPLAB IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its oper-
ation. The functions of these bits are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON register). When interrupt priority is
enabled, there are two bits that enable interrupts glo-
bally. Setting the GIEH bit (INTCON register) enables
all interrupts that have the priority bit set. Setting the
GIEL bit (INTCON register) enables all interrupts that
have the priority bit cleared. When the interrupt flag,
enable bit and appropriate global interrupt enable bit
are set, the interrupt will vector immediately to address
000008h or 000018h, depending on the priority level.
Individual interrupts can be disabled through their cor-
responding enable bits.
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are
compatible with PICmicro mid-range devices. In Com-
patibility mode, the interrupt priority bits for each source
have no effect. The PEIE bit (INTCON register)
enables/disables all peripheral interrupt sources. The
GIE bit (INTCON register) enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt prior-
ity levels are used, this will be either the GIEH or GIEL
bit. High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts, to avoid recursive interrupts.
The "return from interrupt" instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.