PIC18C601/801
DS39541A-page 54
Advance Information
2001 Microchip Technology Inc.
TABLE 4-2:
REGISTER FILE SUMMARY - PIC18C601/801
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS(1)
FFFh
TOSU
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
FFEh
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
FFDh
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
FFCh
STKPTR
STKOVF
STKUNF
—
Return Stack Pointer
00-0 0000
FFBh
PCLATU
—
Holding Register for PC<20:16>
---0 0000
FFAh
PCLATH
Holding Register for PC<15:8>
0000 0000
FF9h
PCL
PC Low Byte (PC<7:0>)
0000 0000
FF8h
TBLPTRU
—
r
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--r0 0000
FF7h
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
FF6h
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
FF5h
TABLAT
Program Memory Table Latch
0000 0000
FF4h
PRODH
Product Register High Byte
xxxx xxxx
uuuu uuuu
FF3h
PRODL
Product Register Low Byte
xxxx xxxx
uuuu uuuu
FF2h
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0E
RBIE
TMR0IF
INT0F
RBIF
0000 000x
0000 000u
FF1h
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—
T0IP
—
RBIP
1111 -1-1
FF0h
INTCON3
INT2P
INT1P
—
INT2E
INT1E
—
INT2F
INT1F
11-0 0-00
FEFh
INDF0
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
N/A
FEEh
POSTINC0
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
N/A
FEDh
POSTDEC0
Uses contents of FSR0 to address data memory - value of FSR0 post-decremented
(not a physical register)
N/A
FECh
PREINC0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented
(not a physical register)
N/A
FEBh
PLUSW0
Uses contents of FSR0 to address data memory -value of FSR0 offset by WREG
(not a physical register)
N/A
FEAh
FSR0H
—
Indirect Data Memory Address Pointer 0 High
---- xxxx
---- uuuu
FE9h
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
uuuu uuuu
FE8h
WREG
Working Register
xxxx xxxx
uuuu uuuu
FE7h
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
N/A
FE6h
POSTINC1
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented
(not a physical register)
N/A
FE5h
POSTDEC1
Uses contents of FSR1 to address data memory - value of FSR1 post-decremented
(not a physical register)
N/A
FE4h
PREINC1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
N/A
FE3h
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 offset by WREG (not a physical register)
N/A
FE2h
FSR1H
—
Indirect Data Memory Address Pointer 1 High
---- xxxx
---- uuuu
FE1h
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
uuuu uuuu
FE0h
BSR
—
Bank Select Register
---- 0000
FDFh
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
N/A
FDEh
POSTINC2
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
N/A
FDDh
POSTDEC2
Uses contents of FSR2 to address data memory - value of FSR2 post-decremented
(not a physical register)
N/A
FDCh
PREINC2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
N/A
FDBh
PLUSW2
Uses contents of FSR2 to address data memory -value of FSR2 offset by WREG (not a physical register)
N/A
FDAh
FSR2H
—
Indirect Data Memory Address Pointer 2 High
---- xxxx
---- uuuu
FD9h
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
uuuu uuuu
FD8h
STATUS
—
NOV
Z
DC
C
---x xxxx
---u uuuu
Legend
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.