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参数资料
型号： PIC18LF6720-I/PT
厂商： Microchip Technology
文件页数： 110/165页
文件大小： 0K
描述： IC MCU FLASH 64KX16 LV 64-TQFP
产品培训模块： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装： 160
系列： PIC® 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 25MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，LVD，POR，PWM，WDT
输入/输出数： 52
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 3.75K x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 12x10b
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 64-TQFP
包装： 托盘
2004 Microchip Technology Inc.
DS39609B-page 47
PIC18F6520/8520/6620/8620/6720/8720
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. The data
memory map is in turn divided into 16 banks of
256 bytes each. The lower 4 bits of the Bank Select
Register (BSR<3:0>) select which bank will be
accessed. The upper 4 bits of the BSR are not
implemented.
The data memory space contains both Special Func-
tion Registers (SFR) and General Purpose Registers
(GPR). The SFRs are used for control and status of the
controller and peripheral functions, while GPRs are
used for data storage and scratch pad operations in the
user’s application. The SFRs start at the last location of
Bank 15 (0FFFh) and extend downwards. Any remain-
ing space beyond the SFRs in the Bank may be imple-
mented as GPRs. GPRs start at the first location of
Bank
0
and
grow
upwards.
Any
read
of
an
unimplemented location will read as ‘0’s.
PIC18FX520 devices have 2048 bytes of data RAM,
extending from Bank 0 to Bank 7 (000h through 7FFh).
PIC18FX620
and
PIC18FX720
devices
have
3840 bytes of data RAM, extending from Bank 0 to
Bank 14 (000h through EFFh). The organization of the
data memory space for these devices is shown in
Figure 4-6 and Figure 4-7.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFF instruction. The
MOVFF
instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
“Access Bank” provides a detailed description of the
Access RAM.
4.9.1
GENERAL PURPOSE
REGISTER FILE
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand. The
operation
of
indirect
addressing
is
shown
in
Section 4.12 “Indirect Addressing, INDF and FSR
Registers”.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as General Purpose
Registers by all instructions. The top section of Bank 15
(F60h to FFFh) contains SFRs. All other banks of data
memory contain GPR registers, starting with Bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 4-2 and Table 4-3.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature. The
SFRs are typically distributed among the peripherals
whose functions they control.
The unused SFR locations are unimplemented and
read as ‘0’s. The addresses for the SFRs are listed in
Table 4-2.
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相关代理商/技术参数
参数描述
PIC18LF6720T-I/PT 功能描述:8位微控制器 -MCU 128KB 3840 RAM 52I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC18LF6721-I/PT 功能描述:8位微控制器 -MCU 128kBF 4096RM 40MHz nonoWatt RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC18LF6721T-I/PT 功能描述:8位微控制器 -MCU 128kBF 4096RM 40MHz nonoWatt RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC18LF6722-I/PT 功能描述:8位微控制器 -MCU 128 KB FL 4K RAM 70 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
PIC18LF6722-I/PT 制造商:Microchip Technology Inc 功能描述:8-Bit Microcontroller IC
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