参数资料
型号: PIC18LF8493-I/PT
厂商: Microchip Technology
文件页数: 35/41页
文件大小: 0K
描述: IC PIC MCU FLASH 8KX16 80TQFP
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 119
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,LCD,POR,PWM,WDT
输入/输出数: 66
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 12x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-TQFP
包装: 托盘
产品目录页面: 643 (CN2011-ZH PDF)
PIC18F6393/6493/8393/8493
DS39896C-page 40
2010 Microchip Technology Inc.
2.8
Use of the ECCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module,
but will still reset the Timer1 (or Timer3) counter.
TABLE 2-2:
REGISTERS ASSOCIATED WITH A/D OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
(3)
PIR1
—ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
(3)
PIE1
—ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
(3)
IPR1
—ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
(3)
PIR2
OSCFIF
CMIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
(3)
PIE2
OSCFIE
CMIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
(3)
IPR2
OSCFIP
CMIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
(3)
ADRESH
A/D Result Register High Byte
(3)
ADRESL
A/D Result Register Low Byte
(3)
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
(3)
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
(3)
ADCON2
ADFM
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
(3)
TRISA
TRISA7(1) TRISA6(1)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
(3)
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
(3)
TRISH(2)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
(3)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2: These registers are not implemented on 64-pin devices.
3: For these Reset values, see the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
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