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参数资料
| 型号： | PIC18LF8723T-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 33/60页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 64KX16 80TQFP |
| 产品培训模块： | Asynchronous Stimulus |
| 标准包装： | 1,200 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，HLVD，POR，PWM，WDT |
| 输入/输出数： | 70 |
| 程序存储器容量： | 128KB（64K x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 3.8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 数据转换器： | A/D 16x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 80-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | PIC18LF8723T-I/PTTR |
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2009 Microchip Technology Inc.
DS39894B-page 39
PIC18F8723 FAMILY
2.6
A/D Conversions
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 2-5 shows the operation of the A/D Converter
after
the
GO/DONE
bit
has
been
set,
the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acqui-
sition time has been selected before the conversion
starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2TCY wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
2.7
Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
FIGURE 2-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 2-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2
μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8
TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY – TAD
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
Conversion starts
b2
b11
b8
b7
b6
b5
b4
b3
b10
b9
On the following cycle:
Discharge
TAD13
TAD12
b0
b1
TAD1
(typically 200 ns)
1
2
3
4
5
6
7
8
13
Set GO/DONE bit
(Holding capacitor is disconnected)
9
12
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
TACQT Cycles
TAD Cycles
Automatic
Acquisition
Time
b0
b11
b8
b7
b6
b5
b4
b1
b10
b9
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
On the following cycle:
TAD1
Discharge
10
11
b3
b2
(typically
200 ns)
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