参数资料
型号: PIC24FJ192GA106T-I/PT
厂商: Microchip Technology
文件页数: 15/18页
文件大小: 0K
描述: IC PIC MCU FLASH 64TQFP
标准包装: 1,200
系列: PIC® 24F
核心处理器: PIC
芯体尺寸: 16-位
速度: 32MHz
连通性: I²C,PMP,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 192KB(65.5K x 24)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
配用: MA240015-ND - BOARD MCV PIM FOR 24F256GA
DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
其它名称: PIC24FJ192GA106T-I/PTTR
PIC24FJ256GA110 FAMILY
DS80368L-page 6
2008-2011 Microchip Technology Inc.
8.
Module: UART (UxERIF Interrupt)
The UART error interrupt may not occur, or occur
at an incorrect time, if multiple errors occur during
a short period of time.
Work around
Read the error flags in the UxSTA register when-
ever a byte is received to verify the error status. In
most cases, these bits will be correct, even if the
UART error interrupt fails to occur. For possible
exceptions, refer to Errata # 9.
Affected Silicon Revisions
9.
Module: UART (FIFO Error Flags)
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
the UART receive interrupt is set to occur when
the FIFO is full or full
(UxSTA<7:6> = 1x), and
more than 2 bytes with an error are received.
In these cases, only the first two bytes with a parity
or framing error will have the corresponding bits
indicate correctly. The error bits will not be set after
this.
Work around
None.
Affected Silicon Revisions
10. Module: SPIx (Enhanced Buffer Modes)
If the SPIx event interrupt is configured to occur
when
the
enhanced
FIFO
buffer
is
full
(SISEL<2:0> = 111), the interrupt may actually
occur when the 7th byte is written to the buffer,
instead of the 8th byte. The other enhanced buffer
interrupts function as previously described.
Work around
Do not use the Full Buffer Interrupt mode. The
SPITBF bit (SPIxSTAT<1>) reliably indicates when
the enhanced FIFO buffer is full, and can be polled
instead of using the Full Buffer Interrupt mode.
Affected Silicon Revisions
11. Module: UART (IrDA)
When the UART is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA endec
(IREN = 1), the module incorrectly transmits a
data payload of 80h as 00h.
Work around:
None.
Affected Silicon Revisions
12. Module: UART (IrDA)
When the UART is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA endec
(IREN = 1), a framing error may occur when
transmitting a data payload of 00h.
Work around:
None.
Affected Silicon Revisions
13. Module: UART (IrDA)
When the UART is operating in 9-bit mode
(PDSEL<1:0> = 1x) and using the IrDA endec
(IREN = 1), the module will incorrectly transmit
10 bits when transmitting data payloads of 00h or
80h.
Work around:
None.
Affected Silicon Revisions
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
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