参数资料
型号: PIC24FJ256GA110T-I/PF
厂商: Microchip Technology
文件页数: 17/18页
文件大小: 0K
描述: IC PIC MCU FLASH 256K100TQFP
标准包装: 1,000
系列: PIC® 24F
核心处理器: PIC
芯体尺寸: 16-位
速度: 32MHz
连通性: I²C,PMP,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 85
程序存储器容量: 256KB(85.5K x 24)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TQFP
包装: 带卷 (TR)
配用: MA240015-ND - BOARD MCV PIM FOR 24F256GA
DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC164323-ND - MODULE SKT FOR 100TQFP
其它名称: PIC24FJ256GA110T-I/PFTR
PIC24FJ256GA110 FAMILY
DS80368L-page 8
2008-2011 Microchip Technology Inc.
18. Module: I2C Module (Master Mode)
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
10-Bit Addressing mode is used (A10M = 1),
and:
the I2C master has the same two upper
address bits (I2CADD<9:8>) as the addressed
slave module.
In these cases, the master also Acknowledges the
address command and generates an erroneous I2C
slave interrupt, as well as the I2C master interrupt.
Work around
Several options are available:
When using 10-Bit Addressing mode, make
certain that the master and slave devices do not
share the same 2 MSBs of their addresses.
If this cannot be avoided:
Clear the A10M bit (I2CxCON<10> = 0) prior to
performing a Master mode transmit.
Read the ADD10 bit (I2CxSTAT<8>) to check
for a full 10-bit match whenever a slave I2C
interrupt occurs on the master module.
Affected Silicon Revisions
19. Module: I2C Module (Slave Mode)
Under certain circumstances, a module operating
in Slave mode may not respond correctly to some
of the special addresses reserved by the I2C
protocol. This happens when the following occurs:
10-Bit Addressing mode is used (A10M = 1),
and
bits, A<7:1>, of the Slave address
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges, ‘1111xxx’ or
‘0000xxx’.
In these cases, the Slave module Acknowledges
the command and triggers an I2C slave interrupt; it
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to ‘1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
20. Module: A/D Converter
When using PGEC1 and PGED1 to debug an
application on any 64-pin devices in this family, all
voltage references will be disabled. This includes
VREF+, VREF-, AVDD and AVSS. Any A/D conversion
will always equal 3FFh.
Work around
Use PGEC2 and PGED2 to debug any A/D
functionality.
Affected Silicon Revisions
21. Module: SPIx (Enhanced Buffer Mode)
In Enhanced Master mode, the SRMPT bit
(SPIxSTAT<7>) may erroneously become set for
several clock cycles in the middle of a FIFO transfer,
indicating that the shift register is empty when it is
not. This happens when both SPIx clock prescalers
are set to values other than their maximum
(SPIxCON<4:2> ≠ 000 and SPIxCON<1:0> ≠ 00).
Work around
Configure the module to generate an SPIx event
interrupt whenever the last bit is shifted out of the
shift register (SPIxSTAT<4:2> = 101). When the
SPIxIF flag becomes set, the shift register is
empty.
Affected Silicon Revisions
A3
A5
A6
X
A3
A5
A6
X
Note:
This issue applies only to 64-pin devices
in
this
family
(PIC24FJ256GA106,
PIC24FJ192GA106
and
PIC24FJ128GA106).
A3
A5
A6
X
A3
A5
A6
X
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