参数资料
型号: PIC24FJ48GA004T-I/ML
厂商: Microchip Technology
文件页数: 12/52页
文件大小: 0K
描述: IC PIC MCU FLASH 48K 44QFN
产品培训模块: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
标准包装: 1,600
系列: PIC® 24F
核心处理器: PIC
芯体尺寸: 16-位
速度: 32MHz
连通性: I²C,PMP,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 35
程序存储器容量: 48KB(16K x 24)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 13x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 带卷 (TR)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164336-ND - MODULE SOCKET FOR PM3 28/44QFN
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
PIC24FJXXXGA0XX
DS39768D-page 2
2008 Microchip Technology Inc.
The regulator provides power to the core from the other
VDD pins. A low-ESR capacitor (such as tantalum) must
be connected to the VDDCORE pin (Figure 2-2 and
Figure 2-3). This helps to maintain the stability of the
regulator. The specifications for core voltage and capac-
FIGURE 2-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
(64/80/100-PIN DEVICES)
FIGURE 2-3:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
(28/44-PIN DEVICES)
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
CEFC
3.3V
Regulator Enabled (ENVREG tied to VDD):
(10
μF typ)
Note 1: These are typical operating voltages. Refer
Timing Requirements” for the full operating
ranges of VDD and VDDCORE.
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
3.3V(1)
2.5V(1)
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
3.3V(1)
2.5V(1)
Regulator Disabled (DISVREG tied to VDD):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
CEFC
3.3V
(10
μF typ)
Regulator Enabled (DISVREG tied to VSS):
Note 1: These are typical operating voltages. Refer
Timing Requirements” for the full operating
ranges of VDD and VDDCORE.
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