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参数资料
| 型号： | PIC24HJ32GP302T-I/SO |
| 厂商： | Microchip Technology |
| 文件页数： | 15/84页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 32K 28SOIC |
| 标准包装： | 1,600 |
| 系列： | PIC® 24H |
| 核心处理器： | PIC |
| 芯体尺寸： | 16-位 |
| 速度： | 40 MIP |
| 连通性： | I²C，PMP，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，DMA，POR，PWM，WDT |
| 输入/输出数： | 21 |
| 程序存储器容量： | 32KB（11K x 24） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 10x10b/12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 包装： | 带卷 (TR) |
| 配用： | AC164339-ND - MODULE SKT FOR PM3 28SOIC |
| 其它名称： | PIC24HJ32GP302T-I/SOTR |
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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
DS70152H-page 22
2010 Microchip Technology Inc.
3.6.4
CodeGuard SECURITY
CONFIGURATION BITS
The FBS, FSS and FGS Configuration registers are
special Configuration registers that control the size and
level of code protection for the Boot Segment, Secure
Segment and General Segment, respectively. For each
segment, two main forms of code protection are
provided. One form prevents code memory from being
written (write protection), while the other prevents code
memory from being read (read protection).
BWRP, SWRP and GWRP bits control write protection
and BSS<2:0>, SSS<2:0> and GSS<1:0> bits control
read protection. The Chip Erase ERASEB command
sets all the code protection bits to ‘1’, which allows the
device to be programmed.
When write protection is enabled, any programming
operation to code memory will fail. When read
protection is enabled, any read from code memory will
cause a ‘0x0’ to be read, regardless of the actual
contents of code memory. Since the programming
executive always verifies what it programs, attempting
to program code memory with read protection enabled
will also result in failure.
It is imperative that all code protection bits are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should any of
the above bits be programmed to ‘0’.
In addition to code memory protection, a part of Data
RAM can be configured to be accessible only by code
resident in the Boot Segment and/or Secure Segment.
The
sizes
of
these
“reserved”
sections
are
user-configurable, using the RBS<1:0> and RSS<1:0>
bits.
3.6.5
BENEFIT OF USER UNIT ID
The dsPIC33F/PIC24H devices provide up to four 8-bit
Configuration registers (FUID0 through FUID3) for the
user to store product-specific information, such as unit
serial numbers and other product manufacturing data.
3.7
Exiting Enhanced ICSP Mode
Exiting Program/Verify mode is done by removing VIH
from MCLR, as illustrated in Figure 3-6. The only
requirement for exit is that an interval P16 should
elapse between the last clock and program signals on
PGCx and PGDx before removing VIH.
FIGURE 3-6:
EXITING ENHANCED
ICSP MODE
Note:
All bits in the FBS, FSS and FGS
Configuration registers can only be
programmed to a value of ‘0’. Bulk Erase
and Segment Erase operations (depend-
ing on the segment) are the only way to
reprogram code-protect bits from ON (‘0’)
to OFF (‘1’).
MCLR
P16
PGDx
PGDx = Input
PGCx
VDD
VIH
P17
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相关代理商/技术参数 |
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|---|---|
| PIC24HJ32GP303-E/ML | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-bit Microcontrollers |
| PIC24HJ32GP303-E/MM | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-bit Microcontrollers |
| PIC24HJ32GP303-E/PT | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-bit Microcontrollers |
| PIC24HJ32GP303-E/SO | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-bit Microcontrollers |
| PIC24HJ32GP303-E/SP | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-bit Microcontrollers |
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