参数资料
型号: PIC32MX340F128L-80I/BG
厂商: Microchip Technology
文件页数: 8/44页
文件大小: 0K
描述: IC MCU 32BIT 128KB FLASH 121XBGA
标准包装: 184
系列: PIC® 32MX
核心处理器: MIPS32? M4K?
芯体尺寸: 32-位
速度: 80MHz
连通性: I²C,IrDA,LIN,PMP,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 121-TFBGA
包装: 托盘
产品目录页面: 649 (CN2011-ZH PDF)
配用: 876-1000-ND - PIC32 BREAKOUT BOARD
Getting Started with PIC32
DS61146B-page 12
2008 Microchip Technology Inc.
Processor core:
MIPS M4K with 5-stage pipeline
MIPS32-compatible Release 2 Instruction Set
MIPS16e Code Compression to improve code density by up to 40%
GPR shadow registers to minimize latency for interrupt handlers
Bit field manipulation instructions
High-performance Multiply/Divide Unit:
- Maximum issue rate of one 32x16 multiply per clock
- Maximum issue rate of one 32x32 multiply every other clock
Static implementation: minimum operating frequency 0 MHz
2.3 to 3.6V operation with full speed over entire range
Low-power modes including RUN, IDLE, and SLEEP
Memory:
Unified 4GB virtual memory space
Fixed Memory Mapping Translation (FMT) mechanism
Flexible partitioning into kernel and user accessible memory segments for
increased application stability
Pre Fetch Cache:
16 lines, each 128-bit wide, instruction Prefetch buffer
Ability to load and lock lines – useful to create SW breakpoints in Flash and
minimize interrupt latency
Interrupt Controller:
Fully programmable interrupt controller with Single or Multi vector mode, support-
ing up to 95 IRQs.
Multiple priorities and subpriorities for each vector
Highest priority interrupt has dedicated register set for reduced interrupt latency
DMA Controller:
Up to 4 independent channels
Memory-to-Memory, Memory-to-Peripheral, and Peripheral-to-Memory transfers
Programmable trigger from any IRQ
Chainable channels, stop on match detection, Auto-Enable mode
Data transfers can occur while the core is in IDLE mode
Integrated programmable CRC engine: calculates on the fly while the data is
transferred.
Enhanced Parallel Master Port:
8- and 16-bit data interface
Up to 16-bit address lines, expandable using GPIO lines
2 Chip Select lines
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