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参数资料
| 型号： | PIC32MX420F032HT-40V/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 147/214页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 32KB FLASH 64TQFP |
| 标准包装： | 1,200 |
| 系列： | PIC® 32MX |
| 核心处理器： | MIPS32? M4K? |
| 芯体尺寸： | 32-位 |
| 速度： | 40MHz |
| 连通性： | I²C，IrDA，LIN，PMP，SPI，UART/USART，USB OTG |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 53 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.3 V ~ 3.6 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 64-TQFP |
| 包装： | 带卷 (TR) |
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PIC32MX3XX/4XX
DS61143H-page 38
2011 Microchip Technology Inc.
3.2
Architecture Overview
The MIPS32 M4K Processor Core contains several
logic blocks working together in parallel, providing an
efficient high performance computing engine. The
following blocks are included with the core:
Execution Unit
Multiply/Divide Unit (MDU)
System Control Coprocessor (CP0)
Fixed Mapping Translation (FMT)
Dual Internal Bus interfaces
Power Management
MIPS16e Support
Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The MIPS32 M4K Processor Core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit general purpose registers used for
integer operations and address calculation. One addi-
tional register file shadow set (containing thirty-two reg-
isters) is added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
32-bit adder used for calculating the data address
Address unit for calculating the next instruction
address
Logic for branch determination and branch target
address calculation
Load aligner
Bypass multiplexers used to avoid stalls when
executing
instructions
streams
where
data
producing instructions are followed closely by
consumers of their results
Leading Zero/One detect unit for implementing the
CLZ
and CLO instructions
Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
Shifter and Store Aligner
3.2.2
MULTIPLY/DIVIDE UNIT (MDU)
The MIPS32 M4K Processor Core includes a multi-
ply/divide unit (MDU) that contains a separate pipeline
for multiply and divide operations. This pipeline oper-
ates in parallel with the integer unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows
MDU operations to be partially masked by system stalls
and/or other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-
bit-wide rs, 15 iterations are skipped, and for a 24-bit-
wide rs, 7 iterations are skipped. Any attempt to issue
a subsequent MDU instruction while a divide is still
active causes an IU pipeline stall until the divide
operation is completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (num-
ber of cycles until a result is available) for the PIC32MX
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
相关PDF资料 |
PDF描述 |
|---|---|
| P51-3000-A-Z-D-4.5OVP-000-000 | SENSOR 3000PSI 1/4-18NPT .5-4.5V |
| REC3-4809DRWZ/H2/A/SMD/CTRL-R | CONV DC/DC 3W 18-72VIN +/-09VOUT |
| REC8-0515DRW/H2/A/M | CONV DC/DC 8W 05VIN +/-15VOUT |
| P51-300-S-O-P-20MA-000-000 | SENSOR 300PSIS 7/16 UNF 4-20MA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PIC32MX430F064H-I/MR | 制造商:Microchip Technology Inc 功能描述:80MHZ, 64KB FLASH, 16 KB RAM, CTMU, I2S, DMA, USB-OTG - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 64KB FLASH 64QFN |
| PIC32MX430F064HT-I/MR | 制造商:Microchip Technology Inc 功能描述:80MHZ, 64KB FLASH, 16 KB RAM, CTMU, I2S, DMA, USB-OTG - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 64KB FLASH 64QFN 制造商:Microchip Technology Inc 功能描述:80MHz, 64KB Flash, 16 KB RAM, CTMU, I2S, DMA, USB-OTG, 64 QFN 9x9x0.9mm T/R |
| PIC32MX430F064HT-I/PT | 制造商:Microchip Technology Inc 功能描述:80MHZ, 64KB FLASH, 16 KB RAM, CTMU, I2S, DMA, USB-OTG - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 64KB FLASH 64TQFP 制造商:Microchip Technology Inc 功能描述:80MHz, 64KB Flash, 16 KB RAM, CTMU, I2S, DMA, USB-OTG, 64 TQFP 10x10x1mm T/R |
| PIC32MX430F064HT-V/MR | 制造商:Microchip Technology Inc 功能描述:80MHZ, 64KB FLASH, 16 KB RAM, CTMU, I2S, DMA, USB-OTG - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 64KB FLASH 64QFN |
| PIC32MX430F064HT-V/PT | 制造商:Microchip Technology Inc 功能描述:80MHZ, 64KB FLASH, 16 KB RAM, CTMU, I2S, DMA, USB-OTG - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 64KB FLASH 64TQFP 制造商:Microchip Technology Inc 功能描述:80MHz, 64KB Flash, 16 KB RAM, CTMU, I2S, DMA, USB-OTG, 64 TQFP 10x10x1mm T/R |
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