参数资料
型号: PIC32MX575F256HT-80I/PT
厂商: Microchip Technology
文件页数: 51/64页
文件大小: 0K
描述: IC MCU 32BIT 256KB FLASH 64TQFP
标准包装: 1,200
系列: PIC® 32MX
核心处理器: MIPS32? M4K?
芯体尺寸: 32-位
速度: 80MHz
连通性: CAN,I²C,SPI,UART/USART,USB OTG
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 53
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
2007-2012 Microchip Technology Inc.
DS61145K-page 55
PIC32MX
REGISTER 19-1:
ECR: EJTAG CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0
R-0
U-0
Rocc
Psz<1:0>
23:16
R-0
R/W-0
R-0
R/W-0
U-0
R/W-0
VPED
Doze
Halt
PerRst
PrnW
PrACC
PrRst
15:8
R/W-0
U-0
R/W-0
U-0
ProbEn
ProbTrap
—EjtagBrk
7:0
U-0
R-0
U-0
DM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 See Note 1
bit 28-24 Unimplemented: Read as ‘0’
bit 23-19 See Note 1
bit 18
PrACC: Pending Processor Access and Control bit
This bit indicates a pending processor access and controls finishing of a pending processor access. A write
of ‘0’ finishes processor access if pending. A write of ‘1’ is ignored. A successful FASTDATA access will clear
this bit.
1
= Pending processor access
0
= No pending preprocessor access
bit 17
Unimplemented: Read as ‘0’
bit 16
See Note 1
bit 15
ProbEn: Processor Access Service Control bit
This bit controls where the probe handles accesses to the DMSEG segment through servicing of processor
accesses.
1
= Probe services processor accesses
0
= Probe does not service processor access
bit 14
ProbTrap: Debug Exception Vector Control Location bit
This bit controls the location of the debug exception vector.
1
= 0xFF200200
0
= 0xBFC00480
bit 13
Unimplemented: Read as ‘0’
bit 12
EjtagBrk: Debug Interrupt Exception Request bit
This bit requests a debug interrupt exception to the processor when this bit is written as ‘1’. A write of ‘0’ is
ignored.
1
= A debug interrupt exception request is pending
0
= A debug interrupt exception request is not pending
bit 11-4
Unimplemented: Read as ‘0’
bit 3
See Note 1
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
For descriptions of these bits, please refer to the EJTAG Control Register Field Descriptions in the “EJTAG
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