参数资料
型号: PIC32MX575F256LT-80I/PF
厂商: Microchip Technology
文件页数: 14/64页
文件大小: 0K
描述: MCU 32BIT 256K FLASH 100TQFP
标准包装: 1,000
系列: PIC® 32MX
核心处理器: MIPS32? M4K?
芯体尺寸: 32-位
速度: 80MHz
连通性: CAN,I²C,SPI,UART/USART,USB OTG
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 85
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TQFP
包装: 带卷 (TR)
2007-2012 Microchip Technology Inc.
DS61145K-page 21
PIC32MX
8.0
CHECK DEVICE STATUS
Before a device can be programmed, the programmer
must check the status of the device to ensure that it is
ready to receive information.
FIGURE 8-1:
CHECK DEVICE STATUS
8.1
4-wire Interface
Four-wire JTAG programming is a Mission mode
operation and therefore the setup sequence to begin
programing should be done while asserting MCLR.
Holding the device in Reset prevents the processor
from executing instructions or driving ports.
The following steps are required to check the device
status using the 4-wire interface:
1.
Set MCLR pin low.
2.
SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
3.
SendCommand
(MTAP_SW_MTAP).
4.
SendCommand
(MTAP_COMMAND).
5.
statusVal = XferData (MCHP_STATUS).
6.
If CFGRDY (statusVal<3>) is not ‘1’ and
FCBUSY (statusVal<2>) is not ‘0’ GOTO step 5.
8.2
2-wire Interface
The following steps are required to check the device
status using the 2-wire interface:
1.
SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
2.
SendCommand
(MTAP_SW_MTAP).
3.
SendCommand
(MTAP_COMMAND).
4.
statusVal = XferData (MCHP_STATUS).
5.
If CFGRDY (statusVal<3>) is not ‘1’ and
FCBUSY (statusVal<2>) is not ‘0’, GOTO
step 4.
SetMode (6’b011111)
SendCommand
(MTAP_SW_MTAP)
SendCommand
(MTAP_COMMAND)
statusVal = XferData (MCHP_STATUS)
FCBUSY = 0
CFGRDY = 1
No
Set MCLR low
4-wire
Done
Yes
Note:
If using the 4-wire interface, the oscillator
source, as selected by the configuration
words, must be present to access flash
memory. In an unprogrammed device, the
oscillator source is the internal FRC allow-
ing for flash memory access. If the config-
uration words have been reprogrammed
selecting an external oscillator source
then it must be present for flash memory
access. See the “Special Features”
chapter in the specific device data sheet
for details regarding oscillator selection
using the configuration word settings.
Note:
If CFGRDY and FCBUSY do not come to
the proper state within 10 ms, the
sequence may
have
been
executed
incorrectly or the device is damaged.
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