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| 型号： | PICREF-1 |
| 英文描述： | SOT-23, Rail-to-Rail Output, Picoamp Input Current Precision Op Amp; Package: SOT; No of Pins: 5; Temperature Range: -40°C to +85°C |
| 中文描述： | PICREF - 2文件 |
| 文件页数： | 6/64页 |
| 文件大小： | 694K |
| 代理商： | PICREF-1 |
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User’s Manual U11377EJ3V0UD
12
3.2.18
VDD0, VDD1 ............................................................................................................................
53
3.2.19
VSS0, VSS1 ............................................................................................................................
53
3.2.20
VPP (
PD78P0308 only).....................................................................................................
53
3.2.21
IC (Mask ROM version only) ...........................................................................................
53
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ............................
54
CHAPTER 4 PIN FUNCTION (
PD780308Y SUBSERIES) ..........................................................
58
4.1
Pin Function List ..............................................................................................................
58
4.1.1
Normal operating mode pins ..........................................................................................
58
4.1.2
PROM programming mode pins (
PD78P0308Y only) ................................................
61
4.2
Description of Pin Functions .........................................................................................
62
4.2.1
P00 to P05, P07 (Port 0) ...................................................................................................
62
4.2.2
P10 to P17 (Port 1) ...........................................................................................................
63
4.2.3
P25 to P27 (Port 2) ...........................................................................................................
63
4.2.4
P30 to P37 (Port 3) ...........................................................................................................
64
4.2.5
P70 to P72 (Port 7) ...........................................................................................................
65
4.2.6
P80 to P87 (Port 8) ...........................................................................................................
66
4.2.7
P90 to P97 (Port 9) ...........................................................................................................
66
4.2.8
P100 to P103 (Port 10) .....................................................................................................
66
4.2.9
P110 to P117 (Port 11) .....................................................................................................
67
4.2.10
COM0 to COM3 ..................................................................................................................
67
4.2.11
VLC0 to VLC2 .........................................................................................................................
67
4.2.12
BIAS ....................................................................................................................................
67
4.2.13
AVREF ...................................................................................................................................
68
4.2.14
AVSS ....................................................................................................................................
68
4.2.15
RESET .................................................................................................................................
68
4.2.16
X1 and X2 ...........................................................................................................................
68
4.2.17
XT1 and XT2 ......................................................................................................................
68
4.2.18
VDD0, VDD1 ............................................................................................................................
68
4.2.19
VSS0, VSS1 ............................................................................................................................
68
4.2.20
VPP (
PD78P0308Y only) ..................................................................................................
68
4.2.21
IC (Mask ROM version only) ...........................................................................................
68
4.3
Pin I/O Circuits and Recommended Connection of Unused Pins ............................
69
CHAPTER 5 CPU ARCHITECTURE ...............................................................................................
73
5.1
Memory Spaces ................................................................................................................
73
5.1.1
Internal program memory space ....................................................................................
76
5.1.2
Internal data memory space ...........................................................................................
77
5.1.3
Special-function register (SFR) area .............................................................................
77
5.1.4
Data memory addressing ................................................................................................
78
5.2
Processor Registers ........................................................................................................
81
5.2.1
Control registers ...............................................................................................................
81
5.2.2
General-purpose registers ..............................................................................................
83
5.2.3
Special-function register (SFR) ......................................................................................
85
5.3
Instruction Address Addressing ...................................................................................
89
5.3.1
Relative addressing ..........................................................................................................
89
5.3.2
Immediate addressing ......................................................................................................
90
5.3.3
Table indirect addressing ................................................................................................
91
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