参数资料
型号: PK60X256VLQ100
厂商: Freescale Semiconductor
文件页数: 60/79页
文件大小: 0K
描述: IC ARM CORTEX MCU 256K 144-LQFP
产品培训模块: Kinetis® Cortex-M4 Microcontroller Family
标准包装: 1
系列: Kinetis
核心处理器: ARM? Cortex?-M4
芯体尺寸: 32-位
速度: 100MHz
连通性: CAN,EBI/EMI,以太网,I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外围设备: DMA,I²S,LVD,POR,PWM,WDT
输入/输出数: 100
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 1.71 V ~ 3.6 V
数据转换器: A/D 33x16b,D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 144-LQFP
包装: 托盘
6. Cb = total capacitance of the one bus line in pF.
SDA
SCL
tHD; STA
tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA
SR
P
S
tHD; STA
tSP
tSU; STO
tBUF
tf
tr
tf
tr
Figure 26. Timing definition for fast and standard mode devices on the I2C bus
6.8.9 UART switching specifications
6.8.10 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 47. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
ns
SD3
tWH
Clock high time
7
ns
SD4
tTLH
Clock rise time
3
ns
SD5
tTHL
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
8.3
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
ns
SD8
tIH
SDHC input hold time
0
ns
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
63
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