参数资料
型号: PKF5611PI
厂商: ERICSSON
英文描述: 5-6 W DC/DC Power Modules Wide Input Series
中文描述: 5-6中西区区议会/ DC电源模块宽输入系列
文件页数: 12/16页
文件大小: 1554K
代理商: PKF5611PI
12
EN/LZT 146 32 R1A (Replaces EN/LZT 137 27 R3) Ericsson Microelectronics, June 2000
Output Voltage Adjust (V
adj
)
Output voltage, V
O
, can be adjusted by using an external resistor.
Typical adjust range is ±15%. If pin 8 and 9 are not connected to-
gether the output will decrease to a low value.To increase V
O
a resis-
tor should be connected between pin 8/9 and 17, and to decrease V
O
a
resistor should be connected between pin 8 and 9 (see fig. 4).
Typical required resistor value to
increase V
O
is given by:
R
adj
= k
1
×(k
2
– V
O
)/(V
O
– V
Oi
), (k )
where
V
O
is the desired output voltage
V
Oi
is the typical output voltage initial setting
and
k
1
=3.18
k
1
=3.18
k
1
=3.18
k
2
=3.86
k
2
=5.93
k
2
=8.05
PKF 5510
PKF 5611
PKF 5617
Typical required resistor value to
decrease V
O
is given by:
R
adj
= k
3
× (V
Oi
–V
O
)/(V
O
– k
4
), (k
where
k
3
=13.0
k
3
=12.6
k
3
=12.6
k
4
=2.75
k
4
=4.28
k
4
=5.95
PKF 5510
PKF 5611
PKF 5617
Voltage Margining
For voltage controlled margining e.g. at final test, the following
setup can be used. By increasing the control voltage V1 to +10V the
output voltage decreases 5% of V
Oi
, and by decreasing V1 to –10V
the output voltage increases 5%.
Capacitive Load
The PKF series has no maximum limit for capacitive load on the out-
put. The power module may operate in current limiting mode during
start-up, affecting the ramp-up and the start-up time. For optimum
start performance we recommend maximum 100 F/A of I
O
. Connect
capacitors at the point of load for best performance.
Input and Output Impedance
Both the source impedance of the power feeding and the load imped-
ance will interact with the impedance of the DC/DC power module.
It is most important to have the ratio between L and C as low as
possible, i.e. a low characteristic impedance, both at the input and
output, as the power modules have a low energy storage capability.
Use an electrolytic capacitor across the input if the source is larger
than 10 H. Their equivalent series resistance together with the
capacitance acts as a lossless damping filter. Suitable capacitor values
are in the range 10–100 F.
Current Limiting Protection (I
lim
)
The output power is limited at loads above the output current
limiting threshold (I
lim
), specified as a minimum value.
Parallel Operation
Paralleling of several converters is easily accomplished by direct
connection of the output voltage terminal pins. The load regulation
characteristic is specifically designed for optimal paralleling per-
formance. Load sharing between converters will be within ±10%. It
is recommended not to exceed P
O
= n × 0.9 × P
Omax
, where P
Omax
is
the maximum converter output power and n the number of paralleled
converters, to prevent overloading any of the converters and thereby
decreasing the reliability performance.
Figure 4
Synchronization (Sync)
It is possible to synchronize the switching frequency to an external
symmetrical clock signal. The input is TTL-compatible and refer-
enced to the input pin 17.
Characteristic
min
typ
max
unit
High level
Threshold level
*)
Low level
Sink current
Sync. frequency
2.2
1.2
0
6.5
2.2
0.4
1.5
688
V
V
V
1.7
mA
kHz
520
*)
Rise time <10ns
Figure 2
Figure 3
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