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参数资料
| 型号： | PL-2507 |
| 英文描述： | PL-2507 USB 2.0 to IDE Bridge Controller Product Datasheet v1.3|Doc - Data Sheet?-- ?PL-2507 Hi-Speed USB 2.0 to IDE Bridge Controller |
| 中文描述： | 特等- 2507的USB 2.0 IDE桥接控制器产品数据表v1.3标准|文件-数据表？ - ？特等- 2507高速USB 2.0 IDE桥接控制器 |
| 文件页数： | 18/19页 |
| 文件大小： | 190K |
| 代理商： | PL-2507 |
Release Date
August 2003
ds_pl2507_v13
PL-2507 Product Datasheet
- 8 -
Document Version 1.3
4.1.3 IDE Interface Related Pins
Table 4-1-3 IDE Interface Related Pins
Symbol
Type
Pin No
Description
DIOWJ
T
14
ATA control. Will be in high impedance state until USB
connection.
DIORJ
T
13
ATA control. Will be in high impedance state until USB
connection.
DMACKJ
T
12
ATA control. Will be in high impedance state until USB
connection.
IORDY
I
10
ATA control.
INTRQ
I
9
ATA control.
DMARQ
I
8
ATA control.
4.1.4 System Pins
Table 4-1-4 System Pins
Symbol
Type
Pin No
Description
REGPWR
P
57
3.3v Power pin for on-chip 3.3v/2.5v regulator
REGGND
P
56
Ground pin for on-chip 3.3v/2.5v regulator
REGVO
P
58
2.5v power output of 3.3v/2.5v regulator
RESETJ
I
38
External reset pin. Low active.
SCL
O
37
Clock pin of two wire serial EEPROM interface
SDA
B
36
Data pin of two wire serial EEPROM interface
TEST
I
39
Chip Test mode enable. It shall be NC or tie to Ground.
SYS_CFG
I
61
System configuration pin. Must always tie to Ground.
RWAKE1J
I
63
Reserved. External signal must be tied to Vcc.
RWAKE0J
I
1
USB Remote Wakeup Enable. Tie to Vcc to disable. Tie
to Ground to enable.
SYS_TEST1
I
7
System test pin. Must tie to Ground.
IDEBLK_EN
I
59
IDE block enable. If low, the ATA control and Data Bus
will all in high impedance state. It shall be set to high for
proper function.
VCC
P
11,32,64
3.3v Power pins
VCCK
P
25
2.5v Power pins
GND
P
16,35,60
Digital ground pins
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