参数资料
型号: PLC18V8ZIAN
厂商: NXP SEMICONDUCTORS
元件分类: PLD
英文描述: Zero standby power CMOS versatile PAL devices
中文描述: OT PLD, 25 ns, PDIP20
封装: 0.300 INCH, PLASTIC, SOT-146-1, DIP-20
文件页数: 16/23页
文件大小: 225K
代理商: PLC18V8ZIAN
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1
1
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M
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
8
9
7
6
5
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2
1
0
8
9
1
1
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1
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1
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D
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1
9
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VNAME
A
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F
F
A
O
CUSTOMER NAME
PURCHASE ORDER #
PHILIPS DEVICE #
CF(XXXX)
CUSTOMER SYMBOLIZED PART #
TOTAL NUMBER OF PARTS
PROGRAM TABLE #
REV.
DATE
NOTES:
In the unprogrammed or virgin state:
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
Pins 1 and 11 are configured as inputs 0 and 9, respectively, via
the configuration cell. The clock and OE functions are disabled.
All output macro cells (OMC) are configured as combinatorial I/O,
with the outputs disabled via the direction control term.
I
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I
*
O
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L
A
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F
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B
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