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参数资料
| 型号： | PLC568 |
| 厂商： | TEMEX COMPONENTS |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 577.52 MHz |
| 文件页数： | 2/2页 |
| 文件大小： | 376K |
| 代理商： | PLC568 |
PLL 567.52 – 577.52 MHz
Fr eq ue ncy
Parameter
Unit
Min.
Typ.
Max.
Comments
Operating Frequency
MHz
567.52
577.52
Lock range
Temperature range
Operating
Deg. C
-10
+85
Storage
Deg. C
-40
+85
Output
Power
dBm
-3
0
+3
Z out
Ohm
50
Return Loss
dB
10
Reference Frequency
Reference Frequency
MHz
15
Input level
Vp-p
0.5
1.0
2.0
Reference input impedance
KOhm
1
Harmonics and spurs
Harmonics
dBc
-20
Spurious at comparison frequency
dBc
-70
Reference freq. breakthrough
dBc
-80
Others spurious
dBc
-80
from 0 to 15 MHz
Lock Detect
Lock detect alarm (High)
Volt
2.5
3.3
Locked
Lock Detect alarm (Low)
Volt
0
0.4
Unlocked
Frequency Lock Time
ms
200
Within ± 1 KHz
Closed Loop Corner Frequency
Hz
500
Closed Loop Peak
dBc
4
Low Pass Frequency Response
Phase Noise
Offset
:
100 Hz
dBc/Hz
-60
Offset
:
1 KHz
dBc/Hz
-75
Offset
:
10 KHz
dBc/Hz
-100
Offset
:
100 KHz
dBc/Hz
-130
Offset
:
1000 KHz
dBc/Hz
-150
Integrated Noise
100 Hz
To
1 MHz
Deg. rms
2.0
Step Size
KHz
5
Power Supply
Chip Supply voltage (Vpll)
Volt
3.15
3.3
3.45
Chip Current
mA
5
VCO Supply voltage (Vvco)
Volt
4.75
5.0
5.25
VCO Current
mA
30
Programming
Standard 3 wire serial , 3.3 volt CMOS , ADF4113 or equivalent
Digital Inputs (High)
Volt
0.8 Vpll
Vpll+0.3
Digital Inputs (Low)
Volt
0.0
0.4
Package
SMP3
Synthesizer : PLC 568
Specification (rev-W0)
April 29
th, 2005
1
TEMEX reserves the right to modify herein specifications and informations at any time when necessary to provide optimum performance and cost.
ELECTRICAL SPECIFICATIONS
MARKING
Manufacturer’s Name:
Yes
Part Number:
PLC 568
Manufacturing date code: Year and Week
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