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参数资料
| 型号： | PLCD5582 |
| 厂商： | SIEMENS A G |
| 元件分类： | 显示用LED |
| 英文描述： | Low Power 0.145” 8-Character, 5x5 Dot Matrix Parallel Input Alphanumeric Intelligent Display |
| 中文描述： | 5X5 DOT MATRIX DISPLAY, HIGH EFFICIENCY RED, 3.68 mm |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 2/12页 |
| 文件大小： | 292K |
| 代理商： | PLCD5582 |
2–132
PLCD5580/1/2/3/4
Maximum Rating
DC Supply Voltage ........................................–0.5 to +7.0 Vdc
Input Voltage Levels Relative
to Ground...............................................–0.5 to V
Operating Temperature ................................. –40
Storage Temperature.................................... –40
Maximum Solder Temperature 0.063"
below Seating Plane, t<5 sec...................................... 260
Relative Humidity at 85
°
C................................................. 85%
Note: Maximum voltage is with no LEDs illuminated.
CC
°
C to +85
C to +100
+0.5 Vdc
°
°
C
C
°
°
C
Enlarged Character Font
Dimensions in inches (mm)
Tolerance: .XXX=
±
.010 (.25)
Write Cycle Timing Diagram
0.100
(2.54)
0.033
(0.84)
typ.
0.011
(0.28)
typ.
0.022
(0.56) typ.
0.145
(3.68)
R0
R1
R2
R3
R4
C0 C1 C2 C3 C4
Tas
Tah
Tceh
Tces
Tw
Tdh
Tds
Tbw
CE
D7-D0
WR
FL, A3-A0
see Notes
Tacc
see Notes
see Notes
see Notes
Notes
1. All input voltages are (V
IL
=0.8 V, V
IH
=2.0 V)
2. These wave forms are not edge triggered.
3. Tbw=Tas + Tah
Switching Specifications
(over operating temperature range and V
CC
=4.5 V).
Symbol
Description
Min.
Units
Tbw
Time Between Writes
30
ns
Tacc
(2)
Display Access Time
130
ns
Tas
Address Setup Time
10
ns
Tces
Chip Enable Hold Time
0
ns
Tah
Address Hold Time
20
ns
Tceh
Chip Enable Hold Time
0
ns
Tw
Write Active Time
100
ns
Tds
Data Valid Prior to
Rising Edge of Write
50
ns
Tdh
Data Hold Time
20
ns
Trc
(1)
Reset Active Time
300
ns
Tclr
(3)
Clear Cycle Time
3
μ
s
1. Wait 300 ns min. after the reset function is turned off.
2. Tacc=Tas + Tw + Tah
3. The Clear Cycle Time may be shortened by writing a
second Control Word with the Clear Bit disabled, 160 ns
after the first control word that enabled the Clear Bit.
The Flash RAM and Character RAM may not be accessed
until the Clear Cycle is complete.
data wait data
write control
word-clear bit
enabled
wait 130 ns
write control
word-clear bit
enabled
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| PLCD5584 | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:Low Power 0.145” 8-Character, 5x5 Dot Matrix Parallel Input Alphanumeric Intelligent Display |
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