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参数资料
| 型号： | PLCD5584 |
| 厂商： | SIEMENS A G |
| 元件分类： | 显示用LED |
| 英文描述： | Low Power 0.145” 8-Character, 5x5 Dot Matrix Parallel Input Alphanumeric Intelligent Display |
| 中文描述： | 5X5 DOT MATRIX DISPLAY, HIGH EFFICIENCY GREEN, 3.68 mm |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 5/12页 |
| 文件大小： | 292K |
| 代理商： | PLCD5584 |
2–135
PLCD5580/1/2/3/4
Top View
Pin Assignment
Cascading the PLCD558X Displays
Pin
Function
Pin
Function
1
RST
28
D7
2
FL
27
D6
3
A0
26
D5
4
A1
25
D4
5
A2
24
D3
6
A3
23
D2
7
Substr. bias
22
No Pin
8
Substr. bias
21
No Pin
9
Substr. bias
20
D1
10
No Connect
19
D0
11
CLKSEL
18
No Connect
12
CLK I/O
17
CE
13
WR
16
GND (logic)
14
V
CC
15
GND (supply)
1
14
28
15
WR FL RST CLK I/O CLKSEL
D0-D7 A0-A4 CE
Display
D0-D7 A0-A4 CE
Up to14 More Displays
in between
Address Decode Chip 1 to 14
15
Address
Data I/O
WR
FL
RST
V
CC
A6
A7
A8
A9
Address
Decoder
WR FL RST CLK I/O CLKSEL
0
Display
TOP VIEW
Pin Function
1
RST
Definition
Used to initialize a display and synchro-
nize blinking for multiple displays
Low input accesses the Flash RAM
Address input LSB
Address input
Address input MSB
Mode selector
Optional connection to V
CC
. Can’t be
used to supply power to display.
See Definition 7
See Definition 7
2
3
4
5
6
7
FL
A0
A1
A2
A3
Substr. bias
8
9
10
11
12
Substr. bias
Substr. bias
No connect
CLKSEL
CLK I/O
Selects internal/external clock source
Outputs master clock or inputs external
clock
A low will write data into the display if CE
is low
Positive power supply input
Analog Ground for LED drivers
Digital Ground for internal drivers
Enables access to the display
13
WR
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
CC
GND
GND
CE
No connect
D0
D1
No pin
No pin
D2
D3
D4
D5
D6
D7
Data input LSB
Data input
Data input
Data input
Data input
Data input
Data input
Data input MSB, selects ROM, page 1
or 2
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