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参数资料
| 型号： | PLL1810A |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, QMA14 |
| 文件页数： | 1/2页 |
| 文件大小： | 72K |
| 代理商： | PLL1810A |
100 Hz
1 kHz
10 kHz
100 kHz
-40
-60
-100
-140
-180
-220
PLL1810A
Telecommunications
Satellite
Telemetry
5
34
1780
-70
2.5
-15
10
5
-40 to +85
Frequency Range
RMS Phase Error (100 Hz - 100 KHz)
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
Package Style
PLL
MHz
°
dBc
mSec
°C
Vdc
mA
Supply Voltage (Vcc, nom.)
Supply Current (Icc, typ.)
All specifications are typical unless otherwise noted and subject to change without notice.
PHASE NOISE (1 Hz BW, typical)
Z-Communications, Inc.
All rights reserved
Page 1
PHASE LOCKED LOOP
FEATURES
APPLICATIONS
PERFORMANCE SPECIFICATIONS
VALUE
UNITS
POWER SUPPLY REQUIREMENTS
APPLICATION NOTES
1780
MHz
Step Size:
50 KHz
- Style Package
PLL
A1
Rev
AN-107 : How to Solder Z-COMM VCOs / PLLs
AN-200 : Mounting and Grounding of Z-COMM PLLs
AN-201 : PLL Fundamentals
AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz<
f
osc<40 MHz
9939 Via Pasar San Diego, CA 92126
TEL (858) 621-2700
FAX (858) 621-2722
Power Output
4±2
dBm
Load Impedance
50
Step Size
50
KHz
HIGH
1840
-
Frequency Range:
-
1840
Charge Pump Output Current
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