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参数资料
| 型号： | PM25LV512-25QCE |
| 厂商： | PMC-Sierra, Inc. |
| 元件分类： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位统一部门，串行闪存 |
| 文件页数： | 5/24页 |
| 文件大小： | 108K |
| 代理商： | PM25LV512-25QCE |
5
Programmable Microelectronics Corp.
Issue Date: December, 2003, Rev: 1.3
PMC
Pm25LV512/010
Pm25LV512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication
term definitions are in the following section.
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave.
TRANSMITTER/RECEIVER:
The Pm25LV512/010 has separate pins designated for data transmission (SO) and
reception (Sl).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CE# going low, the first byte will be received. This byte
contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the Pm25LV512/010, and the serial
output pin (SO) will remain in a high impedance state until the falling edge of CE# is detected again. This will
reinitialize the serial communication.
SERIAL INTERFACE DESCRIPTION
SPI Interface with
(0, 0) or (1, 1)
SDO
SDI
SCK
SCK
SO
SI
Bus Master
CS3
CS2
CS1
CE#
WP# HOLD#
HOLD#
HOLD#
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
SCK
SO
SI
SCK
SO
SI
CE#
WP#
CE#
WP#
Figure 1. Bus Master and SPI Memory Devices
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相关代理商/技术参数 |
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|---|---|
| PM25LV512-25SC | 制造商:PMC 制造商全称:PMC 功能描述:512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory With 25 MHz SPI Bus Interface |
| PM25LV512-25SCE | 制造商:PMC 制造商全称:PMC 功能描述:512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory With 25 MHz SPI Bus Interface |
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