参数资料
型号: PM3350-SW
厂商: PMC-Sierra, Inc.
英文描述: 8 PORT ETHERNET SWITCH
中文描述: 8端口以太网交换机
文件页数: 1/2页
文件大小: 39K
代理商: PM3350-SW
PMC-970277 (P4)
1998 PMC-Sierra, Inc. October, 1998
PM3350
ELAN 8x10
Preliminary
PMC-Sierra,Inc.
8-Port 10 Mbit/s Switch
FEATURES
Single-chip, 8-port, 10BaseT Ethernet
switch device for low-cost unmanaged
and managed networks.
On-chip SmartPath
50 MHz RISC
CPU core, multi-channel DMA
controller, MAC-layer interface logic,
FIFOs, PCI-based expansion port, and
a flexible memory controller.
CPU supports background applications
running on local OS (e.g., SNMP), and
real-time data-oriented applications
(e.g., packet forwarding and filtering
decisions).
Concurrently switches packets
between eight independent, half-
duplex ports at the full Ethernet rate of
10 Mbit/s.
Fully compatible with the PM3351,
1-port 10/100 Mbit/s switch device;
may be used to create a compact and
inexpensive mixed 10/100 Mbit/s
switching hub.
Store-and-forward operation with full
error checking and filtering.
Low-latency operation in both unicast
and broadcast modes.
Filtering and switching at wire rates (up
to 148,8000 packets per second),
supporting a mix of Ethernet and
IEEE 802.3 protocols.
Performs all address learning, address
table management, and aging
functions for up to 32,768 MAC
addresses (limited by external
memory) with an address learning rate
of up to 10,000 addresses per second.
Maximum broadcast/multicast rate of
14,880 packets per second per port
with configurable broadcast storm rate
limiting.
Backpressure flow control with
configurable per-port buffer thresholds
and limits.
Expandable to 64 ports without loss in
throughput using multiple PM3350
devices via an on-chip 1 Gbit/s
expansion port.
Expansion port supports a peak
system bandwidth of 1 Gbit/s, and is
compatible with industry-standard PCI
bus (version 2.1).
Interfaces directly to industry-standard
10BaseT Ethernet Medium Access
Unit devices (LXT944 or similar) with
no glue logic.
Configuration, management, MIB
statistics, and diagnostics available
in-band (via on-chip SNMP agent with
integral TCP/UDP/IP stack).
Maintains and collects per-port and
per-host statistics at wire rates.
Fully static CMOS operation at 50 MHz
clock rates.
Implemented with a 3.3 V core and a
5 V-compatible I/O.
Available in a 256-pin Ball Grid Array
(BGA) package.
BLOCK DIAGRAM
50 MHz
Embedded
RISC CPU
I
Cache
D
Cache
Multi-Channel
DMA
Controller
External
Memory
Interface
EDO DRAM/EPROM
PCI Expansion
Bus
PCI Bus
Interface
Expansion
Registers
FIFO
10BaseT MAC
10BaseT
FIFO
10BaseT MAC
FIFO
10BaseT MAC
FIFO
10BaseT MAC
FIFO
10BaseT MAC
FIFO
10BaseT MAC
FIFO
10BaseT MAC
FIFO
10BaseT MAC
Q
I
10BaseT
10BaseT
10BaseT
10BaseT
Q
I
10BaseT
10BaseT
10BaseT
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