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参数资料
| 型号： | PM37LV512-70JC |
| 厂商： | PMC-Sierra, Inc. |
| 英文描述： | 512 Kbit (64K X 8) Dual-Voltage Multiple-Cycle-Programmable ROM |
| 中文描述： | 512千位（64K的× 8）双电压多周期可编程ROM |
| 文件页数： | 5/17页 |
| 文件大小： | 126K |
| 代理商： | PM37LV512-70JC |
Programmable Microelectronics Corp.
Issue Date: Dec, 2002 Rev: 1.3
PMC
Pm37LV512
BLOCK DIAGRAM
PRODUCT IDENTIFICATION
The hardware product identification mode can be used
by an EPROM programmer to identify the device and
manufacturer for selecting the right programming algo-
rithm
for the device. The product identification mode is
activated by applying 12.0 Volt on A9 pin. For details,
please see Bus Operation Modes in Table 1.
5
WE#
CE#
OE#
COMMAND
REGISTER
CE,OE LOGIC
A0-A15
I/O0-I/O7
I/O BUFFERS
DATA
LATCH
SENSE
AMP
Y-GATING
MEMORY
ARRAY
A
L
Y-DECODER
X-DECODER
BYTE PROGRAMMING
The Pm37LV512 is programmed by using an external
EPROM programmer. The programming mode is acti-
vated by applying 12.0 Volt on OE# pin and V
on CE#
pin. The byte program operation is completed by assert-
ing WE# to low for 20 μs. A chip erase operation is
required prior to program due to a data
“
0
”
can not be
programmed back to a
“
1
”
and only erase operation can
convert
“
0
”
s to
“
1
”
s. The entire chip can be programmed
byte-by-byte by using the byte program algorithmm. Re-
fer to Chart 1. Byte Programming Flowchart and Byte
Program Operations AC Waveforms.
DEVICE OPERATION
READ OPERATION
The access of Pm37LV512 is similar as that of EPROM
or Flash Memory. To obtain data at the outputs, three
control functions must be satisfied:
CE# is the chip enable and should be pulled low
( V
IL
).
OE# is the output enable and should be pulled
low ( V
IL
).
WE# is the write enable and should remains high
( V
IH
)
.
CHIP ERASE
The entire memory array can be erased through a chip
erase operation on an external EPROM programmer.
Pre-program the
“
1
”
s cells in the device is not required
prior to chip erase operation. The chip erase operation
is activated by applying 12.0 Volt to OE# and A9 pins
while CE# pin is low. All other address and data pins
are
“
don
’
t care
”
. Chip erase is completed by asserting
WE# pin to low for 100 ms. The falling edge of WE# will
start the chip erase operation. The device will return back
to standby mode after the completion of chip erase. Refer
to Chart 2. Chip Erase Flowchart and Chip Erase
Operations AC Waveforms.
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