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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
60
mode, the A and B bits in SF mode) for the current superframe before switching to the new
values. This permits signaling integrity to be preserved independent of the superframe alignment
of the T1-XBAS or the signaling data source.
9.27 Bit Oriented Code Generator (XBOC)
The Bit Oriented Code Generator function is provided by the XBOC block. This block transmits
63 of the possible 64 bit oriented codes in the Facility Data Link (FDL) channel in ESF framing
format, as defined in ANSI T1.403-1989. The 64th code (111111) is similar to the HDLC Flag
sequence and is used in the XBOC to disable transmission of any bit oriented codes. When
transmission is disabled the FDL channel is set to all ones.
Bit oriented codes are transmitted on the T1 Facility Data Link channel as a 16-bit sequence
consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated
as long as the code is not 111111. When driving the T1 facility data link the transmitted bit
oriented codes have priority over any data transmitted except for ESF Yellow Alarm. The code to
be transmitted is programmed by writing to the XBOC code registers when it is held until the last
code has been transmitted at least 10 times. An interrupt or polling mechanism is used to
determine when the most recent code written the XBOC register is being transmitted and a new
code can be accepted.
9.28 HDLC Transmitter (TDPR)
The HDLC Transmitter (TDPR) provides a serial data link in the T1 4 kHz ESF facility data link, E1
Sa-bit data link, or in any arbitrary timeslot (T1 or E1). The TDPR is used under microprocessor
control to transmit HDLC data frames. It performs all of the data serialization, CRC generation,
zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message,
a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the TDPR
transmit data FIFO underflows, an abort sequence is automatically transmitted.
When enabled, the TDPR continuously transmits the flag sequence (01111110) until data is ready
to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The
TDPR performs a parallel-to-serial conversion of each data byte before transmitting it.
The default procedure provides automatic transmission of data once a complete packet is written.
All complete packets of data will be transmitted. After the last data byte of a packet, the CRC
word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been
enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the
next packet is available for transmission. While working in this mode, the user must only be
careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128
bytes long. The TDPR will force transmission if the FIFO is filled up regardless of whether or not
the packet has been completely written into the FIFO.
The second procedure transmits data only when the FIFO depth has reached a user configured
upper threshold. The TDPR will continue to transmit data until the FIFO depth has fallen below
the upper threshold and the transmission of the last packet with data above the upper threshold