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参数资料
| 型号： | PM5390 |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | CONNECTOR |
| 中文描述： | ATM NETWORK INTERFACE, PBGA1152 |
| 封装： | 35 X 35 MM, 2.39 MM HEIGHT, FCBGA-1152 |
| 文件页数： | 2/2页 |
| 文件大小： | 100K |
| 代理商： | PM5390 |
Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-2000181 (A2)
Copyright PMC-Sierra,
Inc. 2001. All rights reserved.
SATURN and S/UNI are
registered trademarks and
POS-PHY and PMC-Sierra
are trademarks of PMC-
Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS
’
INTERNAL USE
Advance
PM5390 S/UNI
-9953
Provides egress Ethernet frame
encapsulation (pads to min. size, add
preamble, IFG and CRC generation).
Supports VLAN tagged frames.
Provides eight exact-match address
filters to filter frames based on SA, DA
or VID.
Provides 64-bin hash based algorithm
to filter multicast addresses.
Minimum frame size of 64 bytes.
Provides statistics counters to support
RMON/SNMP.
Supports jumbo frames up to
9.6 Kbytes.
Programmable inter-packet gap (IPG).
Implements in-band PAUSE flow-
control and provides support for out-of-
band flow control.
Upper layer device can flow-control
using dedicated pins or host signaling
to cause generation of a PAUSE
frame.
GENERAL
Provides internal FIFOs (16 KB
ingress, 20 KB egress) to
accommodate system latencies.
Provides line-side and system-side
loopbacks for system level diagnostic
capability.
Provides support for automatic
protection switching (APS) via two 16-
bit LVDS 777.76 MHz ports.
Provides a generic 16-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
Standard 5 signal P1149.1 JTAG test
port.
Low power 1.8 V CMOS core logic with
3.3 V CMOS/TTL compatible digital
inputs and digital outputs.
Industrial temperature range (-40
°
C to
+85
°
C).
1152 pin FCBGA package.
DEVICE INTERWORKING
Other PMC-Sierra devices that
implement the POS-PHY Level 4
interface include:
S/UNI 1x10GE.
S/UNI 10xGE.
S/UNI 9953-POS.
POS-PHY LEVEL 4 INTERFACE
Designed to transmit cells, packets or
frames between physical and data-link
layer devices.
Supports mixed traffic protocols on a
channel by channel basis.
Requires less pins and draws less
power than other 10 Gigabit interface
options.
Compliant with the following
standards:
Optical Internetworking Forum -
System Physical Interface Level 4
Phase II (SPI-4 Phase II).
ATM Forum - Frame Based ATM
Interface Level 4 (ATMF0161.00).
SATURN
POS-PHY
Level 4,
Issue 6, March 2001.
APPLICATIONS
Edge and Core Routers.
Multi-Service (Multi-Protocol)
Switches.
Internet POP and Transport POP L2
Ethernet Switches.
SONET/SDH add/drop multiplexers
and optical cross-connects.
WAN and Edge ATM switches.
Up-link cards.
SONET/SDH ATM/POS and 10
Gigabit Ethernet test equipment.
Emerging DPT, IPT, and GFP
applications.
TYPICAL APPLICATION
10 GIGABIT / OC-192 ROUTER PORT CARD APPLICATION
TT1
Multi-Gbit/s
to Terabit
Switch
Fabric
4 X OC-48 POS Line Card
Optics
S/UNI
9953
Optics
Optics
Optics
Traffic
Manager
IP Processor
1 X OC-192 ATM Interworking Line Card
S/UNI
9953
Integrated
Optics
SAR
IP
Processor
ATM/IP
Inter
Working
Traffic
Manager
2 X OC-192 Ring Access Line Card
GFP or DPT
Ring Access
Controller
IP
Processor
Traffic
Manager
CRSU
4x2488
1 X OC-192 POS / 10 Gigabit Ethernet
Line Card
SFI-4
(Working Mate)
S/UNI
9953
Integrated
Optics
APS Port
1 X OC-192 POS
Line Card
(Protect Mate)
S/UNI
9953
Integrated
Optics
APS Port
Traffic
Manager
L2/L3
Processor
S/UNI
9953
Integrated
Optics
S/UNI
9953
Integrated
Optics
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