参数资料
型号: PMB2304T
厂商: INFINEON TECHNOLOGIES AG
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 220 MHz, PDSO14
封装: PLASTIC, SO-14
文件页数: 2/36页
文件大小: 2613K
代理商: PMB2304T
Functional Description
3 - 3
PMB 2304T
preliminary
Wireless Components
Specification, August 2003
3
EN
3-Line Bus: Enable
Enable line of the serial control with inter-
nal pull-up resistor. When EN = H the
input signals CLK and DA are disabled
internally. When EN = L the serial control
is activated. The received data are trans-
ferred into the latches with the positive
edge of the EN-signal.
4
DA
3-Line Bus: Data
Serial data input with internal pull-up
resistor. The last two bits before the EN-
signal define the destination address. In a
byte-oriented data structure the transmit-
ted data have to end with the EN-signal,
i.e. bits to be filled in (don’t care) are
transmitted first.
5
CLK
3-Line Bus: Clock
Clock line with internal pull-up resistor.
The serial data are read into the internal
shift register with the positive edge (see
pulse diagram for serial data control).
6
V
DD
Positive supply voltage for serial control
logic.
7
MOD
Modulus Control Output for external
dual modulus prescaler. The modulus
output is low at the beginning of the cycle.
When the A-counter has reached its set
value, MOD switches to high. When the
N-counter has reached its set value,
MOD switches to low again, and the cycle
starts from the top. When the prescaler
has the counter factor P or P + 1 (P for
MOD = H, P +1 for MOD = L), the overall
divider factor is NP + A. The value of the
A-counter must be smaller than that of
the N-counter. The trigger edge of the
modulus signal to the input signal can be
selected (see programming tables and
MODA, B) according to the needs of the
prescaler. In single modulus operation
and for standby operation in dual modu-
lus operation, the output is low.
Pin 3
EN
ESD
*2pF
560
75k
Pin 4
DA
ESD
*2pF
560
75k
Pin 5
CL K
ESD
*2pF
560
75k
ES D
2pF
pin 7
MO D
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