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参数资料
| 型号： | PowerPC 403GC |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC结构嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC结构嵌入式控制器） |
| 文件页数： | 1/2页 |
| 文件大小： | 73K |
| 代理商： | POWERPC 403GC |
Highlights
Bus Interface
Direct-connect peripheral/ROM and
DRAM interfaces
Support for 8-, 16- and 32-bit devices
Addressing for main memory storage:
192MB (403GB)
512MB (403GA and 403GC)
External bus master support using the
internal DRAM controller
IEEE 1149.1 (JTAG) compatible
interface, for test, debug and real-time
trace support
DMA Controller
Independent DMA channels:
Four (4) (403GA and 403GC)
Two (2) (403GB)
Buffered, fly-by, memory-to-memory
modes
Programmable for 8-, 16- and
32-bit transfers
Data chaining
Interrupt Controller
Low latency interrupt handling (three
cycles typical)
Six external interrupt inputs (five
regular, one critical)
Dual level interrupt structure
for robust debug
Instruction Fetch, Branch and
Dispatch Unit
Four instruction prefetch queue
Branch folding and static
branch prediction
Dispatches up to two instructions
per cycle
Serial Port (403GA & 403GC only)
RS-232 serial communications
Programmable to 1.5 Mb/s
Memory Protection
Device protection
Address protection
Instruction and Data Caches
Separate 2KB instruction and 1KB
data caches
Two-way set-associative
Fetch-thru instruction cache
Write-back data cache
Timers
56-bit time base (403GA and 403GB)
64-bit time base (403GC)
32-bit programmable interval timer
Fixed interval timer
Watchdog timer for system
error recovery
Power Management Capability
Static low-power design
Dynamic power management
and stand-by mode
Support 3.3V and 5V peripherals
Memory Management Unit
(403GC only)
Memory Management Unit is
precache (cache tags are physical
addresses)
8 page sizes (1K-16M by powers of 4)
for efficient system memory use
64 entry fully associative TLB with
software replacement
16 protection zones
Efficiently designed to minimize
die area
Product Description
PowerPC 403GA*, 403GB* and
403GC* 32-bit RISC Embedded
Controllers combine high performance
and functional integration with low power
consumption. On-chip caches and
integrated device control functions
reduce system chip count and design
complexity, while improving system
throughput.
These embedded controllers execute
programs at sustained speeds
approaching one instruction per cycle.
Their RISC processor cores are tightly
coupled to internal 2KB instruction and
1KB data caches, reducing overhead
for data transfers to and from main
storage. Instruction queue logic
minimizes pipeline stalls by managing
branch prediction, branch folding and
instruction prefetching.
The PowerPC 403GC includes an
integrated MMU featuring a fully
associative TLB. Each entry provides
translation for a memory page, which
can be one of several sizes. TLB
replacement is managed by software,
which can employ the optimum
replacement strategy for a particular
application.
All 403 Embedded Controllers
implement the PowerPC Architecture* in
IBM’s 0.5
μ
m CMOS technology. These
embedded controllers provide
low-power 3.3V operation, with built-in
stand-by mode and dynamic power
management.
PowerPC 403GA, 403GB and 403GC
Embedded Controllers
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