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| 型号： | PS12017-A |
| 厂商： | Powerex Inc |
| 文件页数： | 5/6页 |
| 文件大小： | 0K |
| 描述： | MOD IPM 3PHASE IGBT 1200V 25A |
| 标准包装： | 2 |
| 类型： | IGBT |
| 配置： | 三相反相器 |
| 电流： | 25A |
| 电压： | 1200V |
| 电压 - 隔离： | 2500Vrms |
| 封装/外壳： | 36-DIP 模块 |
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
INA
ELIM
ation
PR
not a its are su
Notic e parame
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e: Th is is tr ic lim
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b
final s pecific ject to cha
nge.
PS12017-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
5
V C
V C –
4 min
max
V C – (200%)
V DH =15V
V DL =5V
T C = – 20 ~ 100?C
500 μ s
3
V C0
0V
V CH (5 μ s)
V CH (505 μ s)
2
V C +(200%)
r CH =
V CH (505 μ s)-V CH (5 μ s)
V CH (5 μ s)
1
Analogue output signal
data hold range
V C +
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
0
–400 –300 –200 –100
0
100 200 300 400
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 μ s delayed point.
Real load current peak value.(%)(I c =I o ! 2)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal V CIN(p) of each phase upper arm
0V
Input signal V CIN(n) of each phase lower arm
0V
Gate signal V o(p) of each phase upper arm
(ASIPM internal)
Gate signal V o(n) of each phase upper arm
(ASIPM internal)
Error output F O1
0V
0V
0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F O ” signal is outputted. After an “input
interlock” operation the circuit is latched. The “F O ” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal V CIN of each phase
upper arm
Short circuit sensing signal V S
0V
Gate signal Vo of each phase
0V
S C delay time
upper arm(ASIPM internal)
Error output F O1
0V
0V
Note : Shor t circuit protection operation. The protection operates with “F O ” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
Jan. 2000
相关PDF资料 |
PDF描述 |
|---|---|
| PS12018-A | MOD IPM 3PHASE IGBT 1200V 25A |
| PS12032 | MOD IPM 3PHASE IGBT 1200V 5A |
| PS12033 | MOD IPM 3PHASE IGBT 1200V 5A |
| PS12034 | MOD IPM 3PHASE IGBT 1200V 10A |
| PS12036 | MOD IPM 3PHASE IGBT 1200V 15A |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PS12018-A | 功能描述:MOD IPM 3PHASE IGBT 1200V 25A RoHS:否 类别:半导体模块 >> 功率驱动器 系列:- 标准包装:15 系列:SPM® 类型:FET 配置:三相反相器 电流:1.8A 电压:500V 电压 - 隔离:1500Vrms 封装/外壳:23-DIP 模块 |
| PS1201E | 制造商:未知厂家 制造商全称:未知厂家 功能描述: |
| PS-12024 | 功能描述:DIN导轨式电源 120W SINGLE OUTPUT RoHS:否 制造商:Mean Well 产品:Linear Supplies 商用/医用:Commercial 输出功率额定值:960 W 输入电压:180 VAC to 264 VAC, 254 VDC to 370 VDC 输出端数量:1 输出电压（通道 1）:48 V 输出电流（通道 1）: 输出电压（通道 2）: 输出电流（通道 2）: 输出电压（通道 3）: 输出电流（通道 3）: 尺寸:150 mm L x 110 mm W |
| PS-120-27P-C | 制造商:MEANWELL 制造商全称:Mean Well Enterprises Co., Ltd. 功能描述:120W Single Output Power Supply or Battery Charger |
| PS12032 | 功能描述:MOD IPM 3PHASE IGBT 1200V 5A RoHS:否 类别:半导体模块 >> 功率驱动器 系列:Intellimod™ 标准包装:15 系列:SPM® 类型:FET 配置:三相反相器 电流:1.8A 电压:500V 电压 - 隔离:1500Vrms 封装/外壳:23-DIP 模块 |
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