参数资料
型号: PS395CPG
厂商: PERICOM SEMICONDUCTOR CORP
元件分类: 多路复用及模拟开关
英文描述: OCTAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDIP24
封装: PLASTIC, DIP-24
文件页数: 4/13页
文件大小: 405K
代理商: PS395CPG
12
PS8462B
01/12/01
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PS395
Precision8-Channel17V,
SPSTSwitchw/SerialControl
CS
DIN
SCLK
CS1
CS2
CS3
SCLK
DIN
To
Other
Serial
Devices
CS
Figure 5. Addressable Serial Interface
FOUR CLOCK
PULSES
SW4
DIN
SCLK
SW0
D4
D0
Figure 6. Differential Multiplexer Input Control
Power-Supply Considerations
Overview
The PS395 construction is typical of most CMOS analog switches.
It has three supply pins: V+, V-, and GND. V+ and V- are used to
drive the internal CMOS switches and to set the limits of the ana-
log voltage on any switch. Reverse ESD-protection diodes are
internally connected between each analog signal pin and both V+
and V-. If any analog signal exceeds V+ or V-, one of these diodes
will conduct. During normal operation, these (and other) reverse-
biased ESD diodes leak, forming the only current drawn from
V+ or V-.
Virtually all the analog leakage current is through the ESD diodes.
Although the ESD diodes on a given signal pin are identical, and
therefore fairly well balanced, they are reverse biased differently.
Each is biased by either V+ or V- and the analog signal. This means
their leakages vary as the signal varies. The difference in the two
diode leakages to the V+ and V- pins constitutes the analog sig-
nal-path leakage current. All analog leakage current flows to the
supply terminals, not to the other switch terminal. This is why
both sides of a given switch can show leakage currents of either
the same or opposite polarity.
There is no connection between the analog signal paths and GND.
V+ and GND power the internal logic and logic-level translators,
and set both the input and output logic limits. The logic-level
translators convert the logic levels to switched V+ and V- signals
to drive the analog signal gates. This drive signal is the only con-
nection between logic supplies (and signals) and the analog sup-
plies. V+, and V- have ESD-protection diodes to GND. The logic-
level inputs and output have ESD protection to V+ and to GND.
The logic-level thresholds are CMOS and TTL compatible when
V+ is +5V. As V+ is raised, the threshold increases slightly. So
when V+ reaches +12V, the threshold is about 3.1V; slightly above
the TTL guaranteed high-level minimum of 2.8V, but still compat-
ible with CMOS outputs.
Bipolar Supplies
The PS395 operates with bipolar supplies between ±3.0V and ±8V.
The V+ and V- supplies need not be symmetrical, but their sum
cannot exceed the absolute maximum rating of 17V. Do not connect
the PS395 V+ to +3V and connect the logic-level pins to TTL
logic-level signals. This exceeds the absolute maximum ratings
and can damage the part and/or external circuits.
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