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| 型号： | PS700-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 14/38页 |
| 文件大小： | 0K |
| 描述： | IC BATTERY MONITOR LI-ION 8TSSOP |
| 标准包装： | 100 |
| 功能： | 电池监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 2.7 V ~ 9 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
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PS700
4.0
MEMORY/OPERATIONAL
REGISTER DESCRIPTION
4.4.1
DCA – DISCHARGE COUNT
ACCUMULATOR
The DCA is a 32-bit register that holds the total
4.1
Memory/Register Map
accumulated capacity discharged from the battery.
Each time a conversion is performed with the sign bit of
The PS700 internal structure is accessible on a strict
memory mapped basis. The only action directly taken
by the PS700 in response to an SMBus command is to
read or write registers, RAM or EEPROM. Any actions
taken by PS700 happen as a result of values written to
internal control registers.
Addressing in PS700 consists of 10 bits plus two bank
select bits. Therefore, there are a total of 4 Kbyte loca-
tions that are addressable within the PS700, organized
as 4 banks of 1024 locations each. Bank 0 is dedicated
to EEPROM, Bank 1 contains RAM/Registers, Bank 2
Ires = 1 and current accumulation is enabled, the
measured value is added to DCA. As a result, the
register is updated whenever a current measurement is
performed with a negative voltage across the sense
resistor (V SR < GND).
The DCA register will rollover if it is allowed be updated
beyond 0xFFFFFFFF, so proper register maintenance
by the host system is necessary. The DCA register may
be cleared using the ACCclr register bit, CLR0,
contains Test registers and Bank 3 is reserved.
4.4.2
DTC – DISCHARGE TIME COUNT
notation is y:0xzzz, where ‘y’ is the bank and ‘zzz’ is the
address in hex.
REGISTER
The DTC records the length of accumulated time that
the battery is in a discharge condition as indicated by a
negative voltage on the SR pin. This register is
4.2
EEPROM
incremented using a 2 Hz internal clock rate; therefore,
The 512-byte EEPROM is located in Bank 0 and
occupies addresses 0:0x000 to 0:0x1FF. All critical
PS700 parameters, calibration factors and learned
data are stored in the PS700 integrated EEPROM. See
can be read using Byte or Block Transfer modes, but
can only be written a byte at a time. Writing the
EEPROM takes approximately 4 ms/byte. An
EEPROM write cycle command from the SMBus is
the DTC is incremented at the rate of 2 counts per
second or 7200 counts per hour so long as current
accumulation is enabled and the Ires register returns a
‘ 1 ’ in the sign bit following a current conversion.
The DTC register will rollover if it is allowed to count
beyond 0xFFFFFFFF; therefore, proper register main-
tenance by the host system is necessary. The DTC reg-
ister may be cleared using the ACCclr register bit,
immediately Acknowledged by the PS700 if no other
EEPROM write cycles are in progress. If a EEPROM
write cycle is attempted while a previous request to
4.4.3
CCA – CHARGE COUNT
ACCUMULATOR
write is in progress, a negative Acknowledge will be
returned until the previous write cycle is completed. A
EEPROM read cycle also results in a negative
Acknowledge or an Acknowledge depending on
whether or not a EEPROM write cycle is in progress
The data EEPROM does not write reliably at tempera-
tures less than 0°C and supply voltages less than 3.3V.
A read or write to a register or RAM location will not be
affected by an EEPROM write cycle in progress.
The CCA is a 32-bit register that holds the total accu-
mulated current delivered as charge into the battery.
Each time a current conversion is performed with the
sign bit of Ires = 0 and current accumulation is enabled,
the measured value is added to CCA. As a result, the
register is updated whenever a current measurement is
performed with a positive voltage across the sense
resistor (V SR > GND).
The CCA register will rollover if it is allowed to be
updated beyond 0xFFFFFFFF; therefore, proper regis-
4.3
General Purpose RAM
ter maintenance by the host system is necessary. The
32 bytes of general purpose RAM are provided as tem-
porary storage and are located in Bank 1 at 1:0x000
through 1:0x01F. The RAM may be read or written
using either the Byte or Block Transfer modes.
CCA register may be cleared using the ACCclr register
bit, CLR2, described below.
4.4
Operational Registers
The following is a detailed description of all operational
registers within the PS700 and all control, status, result
bits and fields that are contained therein.
DS21760F-page 14
? 2004 Microchip Technology Inc.
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