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参数资料
| 型号： | PSD413A1F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可编程逻辑，16K位SRAM,35个可编程I/O,通用PLD有59个输入) |
| 中文描述： | 现场可编程微控制器外围设备与快闪记忆体（可编程逻辑，16K的位的SRAM，35余个可编程输入/输出，通用PLD的有59个输入） |
| 文件页数： | 2/98页 |
| 文件大小： | 365K |
| 代理商： | PSD413A1F |
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PSD413F Family
6-2
ADVANCE INFORMATION
Key Features
(Cont.)
J
Up to 35 I/O Ports.
Each I/O port can be individually configured by the user as standard MCU I/O ports,
PLD I/O, latched address outputs and special function I/O. Two eight-bit I/O ports
can be configured as Open Drain outputs.
J
Two separate non-volatile memory arrays.
Both 1 Mbit (128 Kbytes) of Flash memory and 64 Kbit (8 Kbytes) of Separate OTP
Boot EPROM memory are available. The Boot memory allows for continuous operation
of the MCU while the Flash memory is being written or erased. The Flash memory is
divided into four 32 Kbyte blocks that can be mapped to different address spaces.
Each block is divided into two 16 Kbyte sectors for a total of 8 sectors. Access time is
150 ns which includes address latching and DPLD decoding.
J
Embedded On-Chip Erase and Program Algorithms for the Flash Memory.
Automatically pre-programs and erases the Flash memory or any combination of
sectors. Automatically programs and verifies data at specific address locations in the
Flash memory. Data Polling and a Toggle Bit feature are included for detection of
program or erase cycle completion.
J
Low V
CC
write inhibit <= 3.2 V for the Flash Memory.
J
Sector Protection
Hardware method disables any combination of sectors from program or
erase operation.
J
Minimum 10,000 Erase/Write Cycles.
J
16 Kbit standby SRAM.
Access time is 150 ns which includes address latching and DPLD decoding. The SRAM
can be used as standby storage if standby power is supplied to the Vstby pin. Switching
between V
CC
and Vstby occurs automatically.
J
Page Logic
Page Logic is connected to the ZPLDs and enables address space expansion for
microcontrollers with limited address space capability. Up to 16 pages are available.
J
Security bit.
The security bit prevents reading the PSD configuration, ZPLD and EPROM array
contents. This inhibits copying the device on a programmer.
J
Low power operation.
The Power Management Unit (PMU) enables automatic stand-by modes in the EPROM
and ZPLDs and disables the clock to the ZPLD. Also available is an automatic power
down mode using the ALE signal.
J
68 pin plastic (J-Lead) Chip Carrier (PLDCC) package.
J
Development Tools
Supported by the PSDsoft
TM
MS-Windows
compatible development tools. Includes
PSDabel as the design entry method, an efficient Fitter, and an Address Translator
(see Figure 2).
相关PDF资料 |
PDF描述 |
|---|---|
| PSD413F | Field Programmable Microcontroller Peripherals with Flash Memory(可编程逻辑，16K位SRAM,35个可编程I/O,通用PLD有59个输入) |
| PSD413A2F | Field Programmable Microcontroller Peripherals with Flash Memory(可编程逻辑，16K位SRAM,35个可编程I/O,通用PLD有59个输入) |
| PSD4235G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的闪速在系统可编程外围芯片) |
| PSD4235G2 | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的闪速在系统可编程外围芯片) |
| PSD4235G2 | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD413A2-C-70L | 制造商:WSI 功能描述: |
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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