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| 型号： | PSD4235G2V-B-20B81 |
| 厂商： | 意法半导体 |
| 英文描述： | Tantalum Electrolytic Capacitor; Capacitance:220uF; Capacitance Tolerance:+/- 20 %; Working Voltage, DC:10V; Package/Case:7343-31; Terminal Type:PCB SMT; ESR:0.004ohm; Dielectric Material:Tantalum; Operating Temp. Max:105 C |
| 中文描述： | Flash在系统可编程外设的16位微控制器 |
| 文件页数： | 22/93页 |
| 文件大小： | 503K |
| 代理商： | PSD4235G2V-B-20B81 |
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PSD4000 Series
Preliminary Information
26
The
PSD4000
Functional
Blocks
(cont.)
9.1.2 SRAM
The SRAM is enabled when RS0— the SRAM chip select output from the DPLD— is high.
RS0 can contain up to three product terms, allowing flexible memory mapping.
The SRAM can be backed up using an external battery. The external battery should be
connected to the Vstby pin (PE6). If you have an external battery connected to the
PSD4000, the contents of the SRAM will be retained in the event of a power loss. The
contents of the SRAM will be retained so long as the battery voltage remains at 2V or
greater. If the supply voltage falls below the battery voltage, an internal power switchover
to the battery occurs.
Pin PE7 can be configured as an output that indicates when power is being drawn from the
external battery. This Vbaton signal will be high with the supply voltage falls below the bat-
tery voltage and the battery on PE6 is supplying power to the internal SRAM.
The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using
PSDsoft.
9.1.3 Memory Select Signals
The main Flash (FSi), secondary Flash (CSBOOTi), and SRAM (RS0) memory select
signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules
apply to the equations for the internal chip select signals:
1. Main Flash memory and secondary Flash memory sector select signals must not be
larger than the physical sector size.
2. Any main Flash memory sector must not be mapped in the same memory space as
another Main Flash sector.
3. A secondary Flash memory sector must not be mapped in the same memory space as
another Flash Boot sector.
4. SRAMand I/O spaces must not overlap.
5. A secondary Flash memory sector may overlap a main Flash memory sector. In case of
overlap, priority will be given to the Flash Boot sector.
6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority
will be given to the SRAM, and I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) will automatically address Boot memory segment 0. Any address
greater than 9FFFh will access the Flash memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this
example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
Figure 5 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on
the same level must not overlap. Level one has the highest priority and level 3 has the
lowest.
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