- 您现在的位置：买卖IC网 > PDF目录368226 > PSD4235G3-B-15M (意法半导体) CAP 6.8UF 10V 10% TANT SMD-3216-18 TR-13-PL SN100% PDF资料下载
参数资料
| 型号： | PSD4235G3-B-15M |
| 厂商： | 意法半导体 |
| 英文描述： | CAP 6.8UF 10V 10% TANT SMD-3216-18 TR-13-PL SN100% |
| 中文描述： | Flash在系统可编程外设的16位微控制器 |
| 文件页数： | 18/89页 |
| 文件大小： | 703K |
| 代理商： | PSD4235G3-B-15M |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页
PSD4235G2
18/89
Table 23. PMMR0 Register
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.
Note: Bit Definitions:
APD Enable
0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo
0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK
0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK
0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table 34 for the signals that are blocked on pins CNTL0-CNTL2.
Note: Bit Definitions:
PLD Array Addr
0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL2
0 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1
0 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0
0 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE
0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH
0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
Note: On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express. Bit0 and Bit7 are always cleared on
reset. Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode.
Note: Bit Definitions:
SR_code
0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code
0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_code
0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data
0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data
0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode
0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
PLD
MCells CLK
PLD
Array CLK
PLD
Turbo
not used
(set to 0)
APD
Enable
not used
(set to 0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
PLD
Array WRH
PLD
Array ALE
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to 0)
PLD
Array Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Peripheral
mode
not used
(set to 0)
not used
(set to 0)
FL_data
Boot_data
FL_code
Boot_code
SR_code
相关PDF资料 |
PDF描述 |
|---|---|
| PSD4235G3-B-15MI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G3-B-15U | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G3-B-15UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G3-C-70UI | Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply |
| PSD4235F1V-A-20B81I | CAPACITOR TANT 100UF 10V 20% SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD4256G6V-10UI | 功能描述:CPLD - 复杂可编程逻辑器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全称:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
| PSD-45_11 | 制造商:MEANWELL 制造商全称:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
| PSD-45A-05 | 功能描述:线性和开关式电源 30W 5Vout 6A Input 9.2-18VDC RoHS:否 制造商:TDK-Lambda 产品:Switching Supplies 开放式框架/封闭式:Enclosed 输出功率额定值:800 W 输入电压:85 VAC to 265 VAC 输出端数量:1 输出电压（通道 1）:20 V 输出电流（通道 1）:40 A 商用/医用: 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:Rack 长度: 宽度: 高度: |
发布紧急采购，3分钟左右您将得到回复。