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| 型号： | PSD4235G3-C-70MI |
| 厂商： | 意法半导体 |
| 英文描述： | Solid Tantalum Chip Capacitors / T491 Series - Precision Molded Chip; Capacitance [nom]: 1uF; Working Voltage (Vdc)[max]: 35V; Capacitance Tolerance: +/-10%; Dielectric: Tantalum, Solid; Lead Style: Surface-Mount Chip; Lead Dimensions: 3528-21; Termination: Gold Plated; Body Dimensions: 3.5mm x 2.8mm x 1.9mm; Temperature Range: -55C to +125C; Container: Tape & Reel; Qty per Container: 2,000 |
| 中文描述： | Flash在系统可编程外设的16位微控制器 |
| 文件页数： | 16/89页 |
| 文件大小： | 703K |
| 代理商： | PSD4235G3-C-70MI |
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PSD4235G2
16/89
Table 13.
Enable-Out Registers – Ports A, B, C, F
Note: Bit Definitions (Read-only registers):
Port pin <i>
0 = Port pin <i> is in tri-state driver (default).
Port pin <i>
1 = Port pin <i> is enabled.
Table 14. Input Macrocells – Ports A, B, C
Note: Bit Definitions (Read-only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 15. Output Macrocells A Register
Note: Bit Definitions:
Write Register:
Load MCellA7-MCellA0 with 0 or 1.
Read Register:
Read MCellA7-MCellA0 output status.
Table 16. Output Macrocells B Register
Note: Bit Definitions:
Write Register:
Load MCellB7-MCellB0 with 0 or 1.
Read Register:
Read MCellB7-MCellB0 output status.
Table 17. Mask Macrocells A Register
Note: Bit Definitions:
McellA<i>_Prot
0 = Allow MCellA<i> flip-flop to be loaded by MCU (default).
McellA<i>_Prot
1 = Prevent MCellA<i> flip-flop from being loaded by MCU.
Table 18. Mask Macrocells B Register
Note: Bit Definitions:
McellB<i>_Prot
0 = Allow MCellB<i> flip-flop to be loaded by MCU (default).
McellB<i>_Prot
1 = Prevent MCellB<i> flip-flop from being loaded by MCU.
Table 19. Flash Memory Protection Register
Note: Bit Definitions (Read-only register):
Sec<i>_Prot
1 = Primary Flash memory Sector <i> is write protected.
Sec<i>_Prot
0 = Primary Flash memory Sector <i> is not write protected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
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