参数资料
型号: PSD501B1
英文描述: Field Programmable Microcontroller Peripherals(可编程逻辑,16K位SRAM,40个可编程I/O,通用PLD有61个输入)
中文描述: 现场可编程微控制器外围设备(可编程逻辑,16K的位的SRAM,40余个可编程输入/输出,通用PLD的有61个输入)
文件页数: 1/130页
文件大小: 704K
代理商: PSD501B1
6-1
Key Features
Prelimnary
Programmable Peripheral
PSD5XX Famly
Field-Programmable Microcontroller Peripherals
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Complete family of Field Programmable Microcontroller Peripherals enables the user to
efficiently implement a highly integrated embedded control system in a short time. The
PSD5XX family has a variety of functions such as ZPLDs , I/O Ports, Counter/Timers,
Interrupt Controller, Power Management, EPROM and SRAM.
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“No Glue-Logic” user programmable interface to 8 or 16 bit microcontroller multiplexed
and non-multiplexed bus. The bus control logic can directly decode control signals
generated by 8031, 80196, 80186, 68HC11, 68HC16, 683XX, 16000, Z80, and Z8
architecture. Extended address capability up to 24 bits of address.
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A range of ZPLD (Zero Power PLD) architectures have up to 30 macrocells, 61
inputs and 140 output product terms. Includes 3 functional ZPLDs which enable the
user to efficiently implement a variety of state machines, logic functions, address
decoding and control of the internal PSD5XX functional blocks .
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The ZPLDs use a Zero Power CMOS technology that reduces the device standby
current to 10 μA typical. Unused product terms are disabled to reduce operating power.
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Up to 40 I/O Ports that can be individually configured by the user as standard MCU I/O
ports, PLD I/O, latched address outputs and special function I/O. Two eight bit I/O ports
can be configured as Open Drain Outputs.
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Four 16 bit Counter/Timers, that have 5 modes of operation and can be controlled by the
Peripheral PLD (PPLD) macrocells. Modes of operation are pulse, waveform, time
capture, event counting and watch dog timer (or Real Time Clock). The Counter/Timer
clock input has a prescaler that can scale the input frequency from 4 to 280.
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Eight input priority encoded Interrupt Controller. Four interrupts are generated by the
PPLD and are user defined. The other four interrupts are generated by the
Counter/Timers Terminal Count flags. Each interrupt input can be individually masked
and configured as edge or level sensitive.
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The PSD5XX family contains EPROM densities of 256 Kbit, 512 Kbit and 1 Mbit that can
be configured as 8 or 16 bit data width. The EPROM is divided into 4 equal blocks that
can be mapped to different address spaces. Access time is 70 ns which includes
address latching and Decoder PLD (DPLD) decoding. The EPROM has a low power
mode that is controlled by the CMiser-Bit.
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The PSD5XX family contains a 16Kbit standby SRAM that can be configured as
8 or 16 bit data width. Access time is 70 ns which includes address latching and
Decoder PLD (DPLD) decoding. The SRAM can be used as standby storage if standby
power is supplied to the Vstby pin. Switching between V
CC
and Vstby occurs
automatically.
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Page Logic is connected to the ZPLDs and enables address space expansion of
Microcontrollers with limited address space capability. Up to 16 pages are available.
相关PDF资料
PDF描述
PSD511B1 Field Programmable Microcontroller Peripherals(可编程逻辑,16K位SRAM,40个可编程I/O,通用PLD有61个输入)
PSD502B1 Field Programmable Microcontroller Peripherals(可编程逻辑,16K位SRAM,40个可编程I/O,通用PLD有61个输入)
PSD503B1 Field Programmable Microcontroller Peripherals(可编程逻辑,16K位SRAM,40个可编程I/O,通用PLD有61个输入)
PSD502B1-12U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads
PSD502B1-12UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging
相关代理商/技术参数
参数描述
PSD501B1-12J 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral
PSD501B1-12JI 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral
PSD501B1-12LI 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral
PSD501B1-12U 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral
PSD501B1-12UI 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral